Memory Device Peripheral Layout for Area and IR-Drop Reduction
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Solution Overview
Problem
Existing memory devices face challenges in efficiently utilizing space and managing voltage drop (IR-drop) in standard cells due to varying heights and wasted space in peripheral circuit groups, particularly in switch cells implemented with CMOS transistors.
Innovation Solution
The memory device optimizes the layout by aligning peripheral circuit groups with bit cell groups, using transistors of different types (P-type and N-type) and positioning switch cells with only P-type or N-type transistors in remaining spaces, thereby optimizing area usage and reducing IR-drop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If peripheral circuit groups are designed with varying heights to accommodate different cell types, then functional requirements are met, but area utilization efficiency deteriorates due to wasted space
Solution Approach 1:
The peripheral circuit group is segmented into multiple rows with different heights, where each row can accommodate different types of cells (standard cells, switch cells, buffer cells). This segmentation allows each row to be optimized for its specific function while the overall structure maintains efficient area utilization through compact arrangement.
Solution Approach 2:
The patent introduces a vertical dimension (height variation) to the peripheral circuit group layout, allowing cells to be arranged in multiple rows with different heights. This dimensional change enables better space utilization by accommodating cells of different types in vertically stacked rows rather than requiring uniform height across the entire peripheral circuit group.
2Ease of operation
If switch cells are implemented with CMOS transistors (P-type and N-type), then switching functionality is achieved, but area efficiency deteriorates due to larger cell size
Solution Approach 1:
Different regions of the peripheral circuit group are assigned different cell types based on local functional requirements. Switch cells with P-type and N-type transistors are placed in specific rows where full CMOS functionality is needed, while other rows use simplified cell structures. This local differentiation optimizes area usage by avoiding unnecessary transistors in regions where they are not required.
Solution Approach 2:
Instead of making all cells in the peripheral circuit group as large as the largest cell type (CMOS switch cells), the patent inverts the approach by allowing cells to have different heights and placing them in vertically stacked rows. This inversion of the uniform-height assumption enables compact area utilization while maintaining the necessary switching functionality in specific locations.
3Area of stationary object
If standard cells are aligned with bit cell groups, then area efficiency is improved, but voltage drop (IR-drop) increases due to longer current paths
Solution Approach 1:
The peripheral circuit group is divided into multiple rows segmented by power rail positions. Each row contains cells that are electrically connected to nearby power rails, segmenting the power distribution network into smaller zones. This segmentation reduces the current path length within each zone, thereby reducing IR-drop while maintaining area-efficient alignment with bit cell groups.
Solution Approach 2:
Power rails are strategically positioned to create equipotential regions that minimize voltage drop. Cells in each row are connected to power rails at optimized positions, ensuring that cells requiring high current have nearby power supply connections. This equipotential design maintains area efficiency while reducing the harmful voltage drop effect.
Data Source
AI summary
A memory device includes a first bit cell group including a first plurality of bit cells, and a first peripheral circuit group configured to write data to the first plurality of bit cells and read data from the first plurality of bit cells, where the first peripheral circuit group includes a first type transistor and a second type transistor of a different type from the first type transistor, and where the first peripheral circuit group includes a plurality of first standard cells adjacent to each other in a first direction and a first switch cell including one of the first type transistor and the second type transistor.