Memory Peripheral Circuits for Mixed-Voltage NVM Integration
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Solution Overview
Problem
Integrating peripheral circuits for programmable non-volatile memory, such as sense circuits, level shifters, and low voltage supply detection circuits, with low voltage logic circuits in semiconductor devices is challenging due to the need for higher voltages, which increases fabrication costs.
Innovation Solution
The semiconductor device incorporates core and I/O circuits with n-channel and p-channel metal oxide semiconductor transistors, along with a non-volatile memory and peripheral circuits that operate at different bias potentials, including a low voltage supply detection circuit, level shifter circuit, and sense circuit, utilizing drain-extended MOS transistors to manage voltage levels and facilitate integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If peripheral circuits are designed to operate at high voltage (greater than 6 volts) to program memory cells, then memory programming function is achieved, but integration with low voltage logic circuits (less than 2.0 volts) becomes difficult and fabrication costs increase
Solution Approach 1:
The peripheral circuit is divided into multiple voltage domains: a first voltage domain for high-voltage operations (memory programming) and a second voltage domain for low-voltage operations (logic circuit interfacing). This segmentation allows each domain to operate at its optimal voltage level while being integrated in the same device, resolving the contradiction between achieving high-voltage memory programming and maintaining low-voltage logic circuit compatibility
Solution Approach 2:
Voltage conversion circuits serve as intermediaries between the high-voltage memory cell array and low-voltage logic circuits. These intermediary circuits enable signal and power level translation, allowing the peripheral circuit to interface with both high-voltage memory elements and low-voltage logic without requiring the entire system to operate at high voltage, thus reducing integration complexity and fabrication costs
2Reliability
If peripheral circuits operate at high voltage to program memory, then memory programming capability is enabled, but fabrication costs increase due to the need for high voltage tolerance throughout the device
Solution Approach 1:
Different regions of the peripheral circuit are designed with different voltage tolerance characteristics. The memory interface portion is designed for high-voltage operation to enable programming, while the logic interface portion is designed for low-voltage operation. This local differentiation allows the device to achieve memory programming capability without requiring all components to be fabricated with high-voltage tolerance, thereby reducing fabrication costs
Solution Approach 2:
The peripheral circuit is segmented into high-voltage and low-voltage sections, allowing selective fabrication processes. Only the necessary high-voltage components (such as memory interface circuits) require high-voltage fabrication processes, while other components can use standard low-voltage processes, reducing overall fabrication costs while maintaining memory programming capability
Data Source
AI summary
A semiconductor device includes core circuits configured to operate at a core bias potential, input/output (I/O) circuits configured to operate at an I/O bias potential higher than the core bias potential, and a non-volatile memory having a peripheral circuit configured to operate at a memory program bias potential that is higher than the I/O bias potential. The peripheral circuit is also configured to operate at the core bias potential. The peripheral circuit has an input buffer; a threshold potential at an input buffer input node of the input buffer is less than the core bias potential. The peripheral circuit may be manifested as a low voltage supply detection circuit. The peripheral circuit may be manifested as a level shifter circuit. The peripheral circuit may be manifested as a sense circuit. The input buffer may include a drain extended core transistor to provide the desired threshold potential.