Memory Periphery Tap Cell Layout for Higher Integration Density
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Solution Overview
Problem
The use of individual body terminals for MOSFETs in memory peripheries reduces integration density due to space occupation, and the column of tap cells introduces double diffusion breaks that increase threshold voltage and reduce efficiency.
Innovation Solution
The implementation of tap cells within the bitcell-to-periphery interfaces for biasing the memory periphery, where n-wells and p-wells are divided into regions and biased by n-doped and p-doped tap cells, respectively, reducing the width of tap cells and interfaces to improve integration density and minimize the effect of double diffusion breaks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If individual body terminals are used for MOSFETs in memory peripheries, then latch-up prevention is achieved, but integration density is reduced due to space occupation
Solution Approach 1:
The patent merges the body biasing function into the bitcell structure by integrating tap cells within the bitcell-to-periphery interface regions. This combines the functionality of individual body terminals into a shared biasing mechanism, eliminating the need for separate body terminal connections and thereby increasing integration density while maintaining latch-up prevention through proper body biasing of the periphery transistors
2Productivity
If a column of tap cells is used to bias the periphery, then integration density is increased, but double diffusion breaks are introduced that increase threshold voltage and reduce efficiency
Solution Approach 1:
The patent applies local quality by placing tap cells specifically within the bitcell-to-periphery interface regions rather than forming a continuous column. This localized approach provides the necessary body biasing to the periphery transistors while minimizing the overall tap cell footprint and reducing the impact of double diffusion breaks on threshold voltage by limiting the extent of the doped regions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances integration density and reduces the impact of double diffusion breaks, allowing for a higher number of transistors per unit area of semiconductor die space while maintaining effective latch-up prevention.
Implementation Method 1
A group of neighboring NMOS transistors may have their body biased by a p-doped tap cell (or cells) that ohmically couples to the substrate sufficiently near the group of transistors
Implementation Method 2
The body is thus doped n-type in a PMOS transistor whereas it is doped p-type in PMOS transistor. To prevent latch-up in a PMOS transistor, the body terminal is charged to a power supply voltage
Data Source
AI summary
A memory includes a periphery separated from one or more banks by a bitcell-to-periphery interface. The periphery includes logic circuits for the reading and writing to bitcells within the neighboring banks. Tap cells for the biasing of the periphery extend across the bitcell-to-periphery interface.