Memory Permission Circuitry for Non-Contiguous Address Translation
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Solution Overview
Problem
Current memory management systems face challenges in efficiently managing access to large, non-contiguous physical memory areas while ensuring security and rapid access, particularly in scenarios like video data protection, where stage-two translation is necessary but can lead to memory protection issues due to the large number of non-contiguous regions.
Innovation Solution
The proposed solution involves a memory protection and address translation system with permission circuitry that uses a compact storage of permission data for contiguous regions of the memory address space, allowing for local implementation near the data processing node, and includes a predetermined function for address translation, enabling efficient memory access and protection without relying on extensive main memory references.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If stage-two translation is used for security in virtual machine environments, then information security is improved, but memory access speed deteriorates due to the large number of non-contiguous regions requiring extensive main memory references
Solution Approach 1:
The patent divides the memory address space into multiple contiguous regions, each with its own permission data entry. This segmentation allows the system to manage large non-contiguous memory areas by breaking them into smaller manageable regions that can be quickly accessed without requiring extensive main memory references, thus improving access speed while maintaining security through region-specific permission control
Solution Approach 2:
The patent pre-organizes permission data for multiple contiguous regions in advance, storing it in a structured format that enables rapid lookup. By preparing the permission data structure beforehand with predefined contiguous regions and their associated permissions, the system eliminates the need for extensive runtime main memory references, thereby improving memory access speed while preserving security controls
2Manufacturing precision
If extensive main memory references are used for permission checking in stage-two translation, then memory protection accuracy is improved, but access time increases
Solution Approach 1:
The patent implements local permission data storage for each contiguous region, allowing permission checks to be performed locally without referencing the entire main memory. Each region has its own dedicated permission data that can be quickly accessed and validated, maintaining accurate memory protection while significantly reducing access time by eliminating extensive main memory references
3Reliability
If permission data is stored for each non-contiguous region, then memory protection coverage is improved, but storage complexity increases
Solution Approach 1:
The patent merges multiple non-contiguous memory regions into a set of contiguous regions for permission data storage. By consolidating the permission data structure to work with contiguous regions rather than scattered non-contiguous regions, the system maintains comprehensive memory protection coverage while reducing storage complexity and enabling more efficient data organization and access
Data Source
AI summary
Apparatus comprises input circuitry to receive a translation request defining an input memory address within an input memory address space; and address translation circuitry comprising: permission circuitry to detect whether memory access is permitted for the input memory address with reference to permission data populated from address translation tables and stored in a permission data store for each of a set of respective regions of the input memory address space, there being a dedicated entry in the permission data store for each of the regions so that the input memory address maps to a single respective entry; and output circuitry to provide an output memory address in response to the translation request, in which when the permission circuitry indicates that access is permitted to a region of the input memory address space including the input memory address, the output circuitry is configured to provide the output memory address as a predetermined function of the input memory address.