Memory Integrity Verification via Permitted Read Counter

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Solution Overview

Problem

Existing systems fail to provide continuous memory protection in online computing devices, especially in high-reliability systems that require extended operation without data corruption, as they do not effectively verify memory integrity during normal operation within a demand paged operating system.

Innovation Solution

A method and system that allocate memory segments with a permitted read counter, allowing only one concurrent write and preventing reads during writes to prevent data corruption, while continuously verifying memory integrity without intercepting write operations or modifying the operating system kernel.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If continuous memory verification is implemented in online computing devices, then memory integrity is improved, but system complexity increases

Engineering Contradiction:
Improvememory integrityVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a memory verification module as an intermediary component that operates between the application and the memory device. This module implements the permitted read counter mechanism and coordinates memory access verification without requiring modifications to the operating system kernel or application code, thereby achieving continuous memory integrity verification while minimizing system complexity

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The memory verification module performs self-verification by maintaining a permitted read counter that automatically tracks and validates memory read operations. The module independently manages the verification process, comparing actual read operations against the permitted counter values without requiring external intervention or complex coordination with other system components

Inventive Principle:
Principle #25Self-service

2Reliability

If memory access is restricted through permitted read counter, then data corruption is prevented, but access speed decreases

Engineering Contradiction:
Improvedata integrityVSAvoidmemory access speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent implements preliminary action by pre-establishing the permitted read counter with the expected number of read operations before memory writes occur. This allows the verification module to quickly compare actual reads against pre-calculated permitted values using simple integer comparison, rather than performing complex verification checks during each memory access operation

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The verification mechanism changes the verification parameter from complex data content analysis to simple counter value comparison. By transforming the verification task into comparing integer values (actual read count versus permitted read counter), the system achieves fast verification that minimizes impact on memory access speed while maintaining strong integrity guarantees

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8719538B2Methods and system for ensuring memory device integrity
Publication Date: 2014.05.06 KIDDE FIRE PROTECTION LLC
  • US8719538B2 patent drawing
  • US8719538B2 patent drawing
  • US8719538B2 patent drawing

AI summary

A method for protecting memory segments of a memory device is provided. The method includes receiving, by a processor coupled to the memory device, a request to allocate memory from an application, being executed by the processor, wherein the request includes a requested memory size and allocating, by the processor, a portion of memory having a size greater than the requested memory size. The method also includes creating, by the processor, a permitted read counter associated with the allocated portion of memory, wherein the permitted read counter is initialized to an initial value, and determining, by the processor, whether access to the memory segment is permitted using the permitted read counter. A system for protecting memory segments of a memory device is also disclosed.