Memory I/O Phase Alignment Using Delay Chains and Feedback
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Solution Overview
Problem
Existing memory apparatuses face reliability issues due to varying phase differences between data signals and data strobe signals, particularly in unmatched-type input/output circuits, which are not effectively managed by current methods that rely on memory controllers for re-training, leading to inefficiencies and interruptions in data operations.
Innovation Solution
The memory apparatus includes counters to measure delay times on separate paths for data and strobe signals, comparators to calculate differences, and a delay chain to adjust phase differences independently, compensating for skew without involving the memory controller, thereby maintaining a constant phase difference and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If unmatched-type input/output circuit is used to transmit data signal and data strobe signal without aligning phase difference, then device complexity is reduced, but reliability deteriorates due to varying phase differences
Solution Approach 1:
The memory apparatus independently measures delay times of data signal and data strobe signal through separate paths using counters, calculates phase differences, and adjusts them using delay chains without requiring memory controller intervention. This self-service mechanism maintains reliability while preserving the simplicity of unmatched-type input/output circuits.
Solution Approach 2:
The system continuously monitors the phase difference between data signal and data strobe signal using counters and comparators, then feeds back adjustment commands to delay chains to correct any deviations. This closed-loop feedback ensures reliable data operations while maintaining the simple unmatched-type circuit structure.
2Reliability
If memory controller is involved in skew training and re-training, then phase difference control is achieved, but productivity deteriorates due to interruptions in data operations
Solution Approach 1:
The memory apparatus performs skew training and phase difference adjustment independently using its own counters, comparators, and delay chains, eliminating the need for memory controller involvement. This allows continuous data operations without interruptions, maintaining both reliability and productivity.
Solution Approach 2:
The system performs initial skew training once to establish baseline delay measurements, then uses these pre-established reference values for ongoing phase difference adjustments without requiring repeated controller intervention. This preliminary action enables continuous operation while maintaining control accuracy.
3Productivity
If skew compensation is performed without involving memory controller, then productivity is improved by avoiding interruptions, but device complexity increases due to additional compensation circuits
Solution Approach 1:
The skew compensation function is segmented into independent modular components: counters for delay measurement, comparators for phase difference calculation, and delay chains for adjustment. Each module performs a specific function, allowing the system to achieve continuous operation while keeping individual circuit blocks simple and manageable.
4Device complexity
If phase difference is not precisely controlled, then device complexity is reduced, but manufacturing precision deteriorates in terms of signal timing accuracy
Solution Approach 1:
The system replaces complex mechanical or controller-based phase adjustment mechanisms with electronic delay chains that provide precise timing control through digital delay elements. This substitution achieves high signal timing accuracy while keeping the overall device complexity manageable through integrated circuit implementation.
Data Source
AI summary
A memory apparatus and an operation method of a memory system, the memory apparatus including a first counter that outputs a first count value corresponding to a first delay time of a data strobe signal on a first path; a second counter that outputs a second count value corresponding to a second delay time of a data signal on a second path; a first comparator that outputs a first difference value therebetween; a first register that stores a delay reference value; a second comparator that outputs a second difference value therebetween; and a delay chain that adjusts a phase difference between the data signal and the data strobe signal based on the second difference value.