Memory Module Phase Alignment via Variable Delay Feedback
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Solution Overview
Problem
In high-speed memory modules like DDR5 LRDIMM, the phase relationship between data signals and data strobe signals can change due to environmental variations such as temperature and voltage, potentially leading to incorrect latching operations.
Innovation Solution
A semiconductor device is designed with a first and second data retention circuit, a variable delay circuit, and a timing adjustment circuit. The variable delay circuit generates data strobe signals by delaying the input data strobe signal, and the timing adjustment circuit adjusts the delay amounts based on the match/mismatch determination between the signals from the two data retention circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a variable delay circuit is used to adjust the phase of the data strobe signal, then the phase relationship between data signal and data strobe signal can be adjusted, but the phase relationship may still change due to environmental variations such as temperature and voltage
Solution Approach 1:
The patent implements a feedback mechanism where the timing adjustment circuit continuously monitors the latching operation results and dynamically adjusts the delay amount of the variable delay circuit. This feedback loop ensures that the phase relationship between data signal and data strobe signal is maintained correctly despite environmental variations, resolving the contradiction between reliability and environmental adaptability.
Solution Approach 2:
The patent employs dynamic adjustment of the delay amount based on real-time detection of latching accuracy. The timing adjustment circuit modifies the delay parameters dynamically in response to environmental changes, allowing the system to adapt to temperature and voltage variations while maintaining stable phase relationships.
2Reliability
If the delay time of the decision feedback equalizer changes according to environmental changes, then signal quality enhancement is achieved, but the phase relationship between data signal and data strobe signal may be disrupted
Solution Approach 1:
The timing adjustment circuit uses feedback from latching operation results to compensate for phase shifts introduced by the decision feedback equalizer. By continuously adjusting the delay amount based on detected mismatches, the system maintains phase alignment precision while benefiting from the signal quality enhancement provided by the equalizer.
Solution Approach 2:
The patent dynamically changes the delay parameter of the variable delay circuit in response to environmental variations and equalizer performance. This parameter adjustment allows the system to maintain correct phase relationships while utilizing the decision feedback equalizer for signal quality enhancement.
3Manufacturing precision
If periodic retraining is performed to maintain phase relationship, then latching accuracy is improved, but system complexity and operation time are increased
Solution Approach 1:
The timing adjustment circuit implements a self-service mechanism where the system automatically detects latching accuracy and adjusts its own delay parameters without external intervention or complex periodic retraining sequences. This reduces system complexity while maintaining high latching accuracy through continuous autonomous adjustment.
Solution Approach 2:
The patent maintains continuous adjustment of the delay amount based on real-time latching operation results, eliminating the need for periodic interruptions for retraining. This continuous action ensures sustained latching accuracy without adding significant system complexity or reducing operational time.
Data Source
AI summary
To provide a semiconductor device and a memory module capable of correctly maintaining the phase relationship between a data signal and a data strobe signal that determines the latch timing of the data signal. A variable delay circuit VDLYs_A generates respective data strobe signals DQSin, DQSin_M by delaying an input data strobe signal MDQS by delay amounts ST1, ST2. A timing adjustment circuit TMCT adjusts the delay amount ST1 based on the determination of matching/mismatching between a data signal DQo from a main slicer SLr and a data signal DQo_M from a monitor slicer SLr_M, while changing the delay amount ST2,