Memory Timing Drift Adjustment via Low-Frequency Phase Delay Sensing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Memory systems face timing drift issues due to temperature and voltage variations, causing phase misalignment between timing references in memory devices and controllers, which existing technologies fail to accurately detect and adjust for during normal data transport.
Innovation Solution
A memory system that uses a low-frequency slow clock signal to determine phase delays in the memory device, allowing for accurate drift detection and phase adjustment of high-frequency clock signals used for data transport, thereby maintaining synchronization despite temperature and voltage changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high-frequency clock signal is used for data transport, then data transport speed is improved, but timing drift detection accuracy deteriorates due to phase alignment issues
Solution Approach 1:
The patent applies preliminary action by performing timing drift calibration using a low-frequency clock signal before actual high-speed data transport. The memory controller calibrates the phase relationship between clock signals during idle periods or power-up phases, storing calibration data that compensates for timing drift during subsequent high-speed operations. This allows accurate drift detection to be achieved indirectly through preliminary low-frequency calibration, resolving the contradiction between high-speed data transport and timing drift detection accuracy.
2Reliability
If continuous calibration is performed to maintain synchronization, then timing synchronization is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic action by performing calibration only at specific intervals rather than continuously. The memory controller conducts timing drift calibration during power-up, after power-down events, or at predetermined intervals during operation. Between calibration events, the system operates in a low-power mode using the stored calibration data, thereby maintaining timing synchronization reliability while significantly reducing power consumption compared to continuous calibration approaches.
3Use of energy by moving object
If phase adjustment is performed during power save mode, then power consumption is reduced, but timing drift compensation capability is limited
Solution Approach 1:
The patent applies copying by creating a low-frequency copy of the clock signal for calibration purposes. Instead of using the full-speed high-frequency clock signal that would consume excessive power, the system generates and calibrates using a down-sampled or divided-frequency clock signal that mimics the timing characteristics but operates at lower power. This copied low-frequency signal enables phase relationship calibration during power-save modes while maintaining the ability to compensate for timing drift in the actual high-frequency data transport operations.
Data Source
AI summary
A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.