Memory Controller Phase Alignment Using Returned Error Correlation
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Solution Overview
Problem
Conventional memory systems face challenges in aligning the phase of data transmission with the internal clock of a memory circuit, especially at higher data rates, due to the lack of mechanisms for determining the phase relationship between the memory controller and the DRAM, which can lead to errors in data transfer.
Innovation Solution
A memory controller system that uses a masking circuit and error detection circuit to calculate error results from both the memory controller and the memory circuit, allowing for the adjustment of data transfer timing based on correlation information to align with the internal clock of the memory circuit without accessing memory elements, thereby reducing the need for periodic phase training and minimizing retraining time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional phase training methods are used to align data transmission phase with memory circuit clock, then phase alignment is achieved, but system operation is disrupted due to periodic retraining requirements
Solution Approach 1:
The patent implements a feedback mechanism where the memory circuit returns error information to the memory controller, enabling continuous phase alignment adjustment without disrupting system operation. The error information serves as feedback that allows the controller to maintain optimal phase alignment dynamically.
Solution Approach 2:
The memory circuit performs self-diagnosis by calculating error information internally and returning it to the controller. This self-service capability eliminates the need for external training sequences, allowing phase alignment to be maintained without stopping normal memory operations.
2Measurement precision
If functional tests with data patterns are performed for phase training, then phase alignment is achieved, but retraining time is increased
Solution Approach 1:
The patent extracts only the essential error information needed for phase alignment from complex training sequences. By using error information returned during normal operations rather than performing complete functional tests, the retraining time is significantly reduced while maintaining alignment precision.
Solution Approach 2:
Instead of performing complete functional tests with data patterns, the patent uses partial error information from normal memory operations to achieve phase alignment. This partial action approach reduces retraining time while still providing sufficient information for precise alignment.
3Measurement precision
If write-to-read bus turnarounds are performed for phase training, then phase alignment is achieved, but system bandwidth is reduced
Solution Approach 1:
The patent enables continuous error information collection during normal read/write operations without requiring separate training transactions. This continuity eliminates bus turnaround overhead and maintains full system bandwidth while achieving phase alignment through the returned error information.
Data Source
AI summary
Methods and apparatus for adjusting a phase difference between clock signals. A first clock signal at a memory controller is adjusted relative to a clock second signal at a memory device. In one embodiment, data is transferred to the memory device according to the first clock signal, which has a predetermined phase relationship with second clock signal. Data received at the memory device is sampled at the memory device according to the second clock signal. Analysis is done of the data on the memory controller and of the received data on the memory circuit. On the basis of the analysis, an adjustment may be made to the phase relationship.