3D Memory Phase Synchronization via Reception Block Delay Control
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Solution Overview
Problem
In 3D semiconductor apparatuses, signal phase control is challenging due to delays caused by long transmission distances, process variations, and temperature changes, which affect the synchronization of signals between stacked memory chips.
Innovation Solution
A semiconductor apparatus with a logic memory chip and stacked memory chips, where each memory chip includes reception blocks that receive input signals and strobe signals, allowing for phase control by setting delay amounts to synchronize the signals, thereby controlling phase differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If memory chips are vertically stacked to improve integration density, then area efficiency is improved, but signal transmission distance increases causing phase delay
Solution Approach 1:
The patent applies preliminary action by performing phase calibration before normal operation. The transmission block outputs signals with predetermined phase relationships, and the reception block预先 sets delay amounts based on expected transmission characteristics, so that when signals are transmitted through the stacked memory chips, the phase delays are already compensated for, ensuring synchronized reception without real-time adjustment overhead.
Solution Approach 2:
The patent changes the delay parameter dynamically. The reception block includes a delay control unit that adjusts delay amounts based on calibration results. During calibration mode, the system determines optimal delay values, then applies these parameter changes in normal mode to compensate for phase delays caused by vertical stacking, thus maintaining signal synchronization despite increased transmission distance.
2Reliability
If phase control is implemented to synchronize signals, then signal synchronization is improved, but device complexity increases
Solution Approach 1:
The patent segments the phase control function into separate blocks: a transmission block in the first memory chip that outputs signals with controlled phase relationships, and a reception block in the second memory chip that applies delay compensation. This segmentation distributes the complexity across multiple modules rather than concentrating it in a single complex controller, making the system more manageable and easier to implement in standardized memory chip architectures.
Solution Approach 2:
The patent implements feedback through a calibration mode. The reception block receives signals, compares their phases, and feeds back delay adjustment information to the delay control unit. This feedback mechanism allows the system to automatically determine optimal delay values and adjust accordingly, reducing the need for manual tuning and external intervention, thus improving reliability while keeping the control mechanism relatively simple.
3Measurement precision
If delay compensation is applied to correct phase differences, then signal accuracy is improved, but processing time increases
Solution Approach 1:
The patent applies preliminary action by performing phase calibration once during initialization or setup, rather than continuously during normal operation. The delay control unit预先 determines optimal delay amounts and stores them for reuse. This approach achieves high phase accuracy without incurring continuous processing time penalties, as the delay compensation parameters are established in advance and then applied statically during data transmission.
Solution Approach 2:
The patent uses periodic action by implementing calibration in a separate calibration mode that operates periodically or on-demand rather than continuously. The system switches between calibration mode (for determining delay values) and normal mode (for data transmission with applied delays). This periodic calibration approach ensures phase accuracy is maintained without continuously consuming processing time, as the bulk of operation occurs in the efficient normal mode with pre-determined delay parameters.
Data Source
AI summary
A semiconductor apparatus includes a logic memory chip including a transmission block which outputs input signals and a strobe signal; and a plurality of memory chips stacked with the logic memory chip. At least one of the plurality of memory chips includes a plurality of reception blocks. Each of the plurality of reception blocks receives an input signal among the input signals and the strobe signal, and controls a phase of any one of the input signal and the strobe signal.