Memory PHY Power Gating with Early Command Signals
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory systems face a challenge in reducing power consumption without increasing latency during memory read access, as transitioning from low power states to active states is inefficient due to long exit latency, which affects performance and user experience.
Innovation Solution
Implementing command clock gating and RXBias gating circuitry in the memory PHY, where an early command indication signal and a read indication signal are used to enable the clock network and receiver bias circuitry before receiving commands from the memory controller, reducing power consumption without increasing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If memory subsystem transitions to low power state, then power consumption is reduced, but exit latency increases significantly
Solution Approach 1:
The patent applies preliminary action by enabling the clock network and receiver bias circuitry in advance using early command indication signals before actual memory read commands are received. This pre-enabling allows the memory PHY to exit low power state proactively, reducing the effective exit latency experienced by workloads while still allowing the system to enter low power state during idle periods.
2Loss of time
If memory PHY remains in active state, then read access latency is reduced, but power consumption increases
Solution Approach 1:
The patent implements periodic action by dynamically transitioning the memory PHY between low power and active states based on periodic monitoring of command queues and early command indication signals. The system periodically enters low power state during idle periods and periodically activates before expected read commands, creating a rhythm of power state transitions that balances power savings with latency requirements.
Solution Approach 2:
The patent applies dynamics by making the memory PHY power state flexible and adaptive rather than static. The system dynamically adjusts its power state based on workload characteristics, using early command indication signals to predict when activation is needed and transitioning states accordingly. This dynamic approach allows optimization of both power consumption and latency based on real-time conditions.
Data Source
AI summary
Memory power consumption is reduced without increasing latency of memory read access. When inactive, power consumption is reduced in a PHY in a memory controller by disabling receiver bias circuitry and a clock network in the PHY. The memory controller sends two command-based signals to the PHY to enable the PHY to enable the receiver bias circuitry and the clock network in the PHY to transition the memory from a low power state to an active power state prior to or at the time of receiving command from the memory controller. A first command-based signal is an early command indication signal that is sent before any command. The second command-based signal is a read indication signal that is sent synchronous with every read command. Upon receiving these signals, the PHY enables the clock network and receiver bias circuitry.