Memory PHY Power Gating for Low-Leakage Idle States
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Solution Overview
Problem
Conventional power management techniques for memory physical layers in computing devices result in high leakage power consumption, as the power supply remains connected to the memory PHY even when it is inactive, reducing battery life without effectively managing power usage.
Innovation Solution
Implementing power gating by disconnecting the power supply from a portion of the memory PHY during inactivity and using save/restore signals to maintain data integrity, transitioning into and out of an enhanced low power state with minimal latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the power supply remains connected to the memory PHY during inactivity, then data integrity is maintained, but leakage power consumption increases
Solution Approach 1:
The memory PHY is divided into multiple independent power domains, allowing selective power gating of specific sub-blocks (such as PLL, CDR, equalization circuits) while keeping other parts active. This segmentation enables precise control of power consumption without compromising the entire PHY's data integrity functionality.
Solution Approach 2:
Save/restore circuits are activated before power gating occurs to capture the current state of the memory PHY. These circuits preserve critical data and configuration information in backup storage elements, ensuring that when power is restored, the PHY can resume operation without data loss or corruption.
2Loss of energy
If the power supply is disconnected from the memory PHY during inactivity, then leakage power is reduced, but transition latency increases
Solution Approach 1:
The power gating control mechanism is merged with the existing memory controller and PHY state machine. This integration allows the system to anticipate power transition needs and coordinate save/restore operations with memory access patterns, thereby minimizing the impact on transition latency while achieving significant leakage power reduction.
3Duration of action of moving object
If power gating is implemented in the memory PHY, then battery life is extended, but system complexity increases
Solution Approach 1:
The memory PHY incorporates self-managing power gating capabilities where internal state detectors automatically identify when power gating is appropriate, and embedded save/restore circuits autonomously preserve and restore data without requiring complex external control logic. This self-service approach extends battery life while minimizing the increase in system complexity.
Data Source
AI summary
In accordance with the described techniques, a device includes a host processor, a memory, and a memory physical layer. The memory physical layer enters an enhanced low power state in which a power supply is disconnected from a portion of the memory physical layer while the memory is inactive with respect to servicing memory requests of the host processor. In addition, the memory physical layer exits the enhanced low power state responsive to the memory being active with respect to servicing memory requests of the host processor and/or at least one memory request being enqueued for servicing by the memory.