Memory PHY Core Logic Power Switching for Low-Power States

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Solution Overview

Problem

Existing electronic devices face inefficiencies in low power operating states, including noticeable electrical power losses and slow transitions, due to voltage regulators being provisioned for maximum power loads and inefficient operation at reduced voltages.

Innovation Solution

The electronic device employs a dual-voltage regulator system, where the memory PHY voltage regulator provides power at full power states and the system voltage regulator takes over for low power states, with a controller managing transitions based on memory access activity and idleness to optimize power usage and reduce dynamic power losses.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If voltage regulators are provisioned for maximum power loads, then full power operation is efficient, but low power operation experiences noticeable electrical power losses

Engineering Contradiction:

Improvefull power operation efficiencyVSAvoidelectrical power losses in low power states

Core Design Contradiction:

PowerVSLoss of energy

Solution Approach 1:

The patent divides the voltage regulation function into two separate regulators: a first voltage regulator optimized for full power operation and a second voltage regulator optimized for low power operation. This segmentation allows each regulator to be provisioned for its specific operating range, eliminating the energy losses that occur when a single regulator designed for maximum power is used at low power levels.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system dynamically switches between the first and second voltage regulators based on the operational state of the core logic. When the core logic transitions between full power and low power modes, the controller相应地 switches between regulators, ensuring that the appropriate regulator is always active to maintain efficiency across different power levels.

Inventive Principle:

Principle #15Dynamics

2Use of energy by moving object

If low power operating states are used to conserve electrical power, then power consumption is reduced, but transitions between states are slow and require significant effort

Engineering Contradiction:

Improveelectrical power consumptionVSAvoidtransition delay between operating states

Core Design Contradiction:

Use of energy by moving objectVSLoss of time

Solution Approach 1:

The patent maintains the core logic in a low power operating state by keeping it powered by the second voltage regulator even when not actively transmitting data. This preliminary action of staying in low power mode eliminates the need for lengthy transitions from high power states, reducing both the time and energy required to enter low power states while maintaining the ability to quickly resume full power operation when needed.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS11567557B2Electrical power operating states for core logic in a memory physical layer

Publication Date: 2023.01.31 ADVANCED MICRO DEVICES INC

AI summary

An electronic device has a memory functional block that includes memory circuits and a memory physical layer (PHY) functional block with core logic that controls operations in the memory functional block, a memory PHY voltage regulator, a system voltage regulator, and a controller. The electronic device also includes a switch having an input coupled to an output of the memory PHY voltage regulator, another input coupled to an output of the system voltage regulator, and an output coupled to a power supply input of the core logic. The controller sets the switch so that electrical power is provided from the memory PHY voltage regulator to the core logic in a full power operating state. The controller sets the switch so that electrical power is provided from the system voltage regulator to the core logic in one or more low power operating states.