Memory PHY Wake-Up Parallelism for Fast Self-Refresh Exit
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Solution Overview
Problem
Existing memory subsystem power management systems face inefficiencies due to high exit latency from low power states, particularly self-refresh, which negatively impact performance and user experience.
Innovation Solution
A memory subsystem architecture that powers up the physical interface in parallel with the memory device exiting self-refresh, using a slower clock path to send the self-refresh exit command before fully powering up the high-speed clock path, thereby reducing power consumption and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the system enters self-refresh state to save power, then power consumption is reduced, but exit latency increases significantly
Solution Approach 1:
The patent applies preliminary action by initiating the PHY power-up sequence before the memory device exits self-refresh. The memory controller sends a wake-up command to the PHY while the memory device is still in self-refresh state, so that the PHY is fully powered and ready to receive data immediately when the memory device exits, eliminating the serialization delay between PHY power-up and memory exit.
Solution Approach 2:
The patent implements skipping by allowing the memory device to exit self-refresh and start transferring data to the host before the PHY is completely powered up. The system tolerates the PHY being in a transitional power state during the initial data transfer, thus skipping the requirement to wait for complete PHY initialization and significantly reducing exit latency.
2Use of energy by moving object
If the system enters low power state with PLL and voltage rails powered down, then power consumption is minimized, but exit latency becomes too great for effective use
Solution Approach 1:
The patent applies preliminary action by pre-powering the PHY interface before the memory device enters self-refresh. The memory controller initiates a controlled power-down sequence for the PHY that maintains essential circuitry in a low-power but quickly-recoverable state, rather than a complete power-off. This allows the PHY to be restored rapidly when exiting the low-power state, reducing exit latency to acceptable levels while still achieving significant power savings during the low-power state.
Data Source
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AI summary
In a memory subsystem, a memory controller can put its physical interface (PHY) into a low power state when an associated memory device is in self-refresh. Instead of powering on the interface and then triggering the memory device to exit self-refresh, or instead waiting for the physical interface to be powered up prior to waking the memory device from self-refresh, the memory controller can instruct the PHY to send a self-refresh exit command to the memory device and power up the physical interface in parallel with the memory device coming out of self-refresh. The memory controller can power down a high speed clock path of the PHY and use a slower clock path to send the self-refresh exit command before powering the high speed clock path back up.