High-Speed Memory PHY Read Training via Asynchronous FIFO
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Solution Overview
Problem
High-speed memory read training processes, such as those in HBM3, face challenges due to time differences between data and strobe signals, leading to increased power consumption and prolonged training times.
Innovation Solution
A physical layer is introduced between the high-speed memory and the memory controller, comprising an analog physical layer with RDQS and DQ delay units, and a digital physical layer with an asynchronous FIFO and validity signal forming unit, which adjusts signal phases, samples DQ signals with RDQS, and generates validity signals without the need for preamble and postamble removal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a cleaning block is used to remove preamble and postamble from RDQS signal, then read training can be performed, but power consumption increases and training time increases
Solution Approach 1:
The patent extracts and removes the preamble and postamble portions from the RDQS signal, retaining only the useful data portion. This is achieved through signal processing that identifies and isolates the valid data region, eliminating the need for complex cleaning blocks while reducing power consumption and training time.
Solution Approach 2:
Instead of processing the entire RDQS signal including preamble and postamble, the patent applies partial action by focusing only on the useful data portion. This selective processing approach reduces the computational burden and power consumption while maintaining read training reliability.
2Reliability
If a cleaning block operates at high frequency to remove preamble and postamble, then read training can be performed, but device complexity increases
Solution Approach 1:
The patent extracts only the necessary signal processing functions needed to remove preamble and postamble, eliminating unnecessary components. This results in a simplified architecture that maintains read training reliability while reducing device complexity.
Solution Approach 2:
The patent employs a multi-functional approach where the signal processing unit performs multiple functions including preamble and postamble removal, timing adjustment, and data validation. This consolidation reduces the number of separate components needed, thereby reducing device complexity.
3Speed
If read training is performed with high frequency signals, then data can be read at high speed, but training time increases
Solution Approach 1:
The patent performs preliminary actions by pre-processing the RDQS signal to remove preamble and postamble before the main read training process. This preparation step reduces the amount of data that needs to be processed during training, thereby reducing training time while maintaining high data read speed.
Solution Approach 2:
The patent skips the unnecessary processing of preamble and postamble portions, focusing only on the useful data. This selective processing approach allows the training to rush through the essential data validation more quickly, reducing overall training time while maintaining high read speed.
Data Source
AI summary
The present embodiment provides a physical layer (PHY) between a high-speed memory and a memory controller, including: an analog physical layer including a read data strobe (RDQS) delay unit that delays an RDQS signal of the high-speed memory and outputs the delayed RDQS signal and a data (DQ) delay unit that delays DQ signals and outputs the delayed DQ signals; and a digital physical layer including an asynchronous first-in first-out (FIFO) that samples the DQ signal with the RDQS signal and outputs the DQ signal, a DQ arrangement block that rearranges the DQ signal, and a validity signal forming unit that forms a validity signal indicating validity of data from data output from the asynchronous FIFO, in which the analog physical layer receives a clock having the same frequency as the high-speed memory and operates, and the asynchronous FIFO and the validity signal forming unit receive a clock having a lower frequency than the clock provided to the high-speed memory and operate.