3D Memory Pillar Layout for Smaller Array Footprint
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Solution Overview
Problem
There is a demand for a memory device with a smaller area size, as existing three-dimensional memory devices face challenges in reducing their footprint while maintaining structural integrity and efficiency.
Innovation Solution
The memory device incorporates a configuration with memory pillars arranged in a staggered array, supported by larger diameter support pillars and contact plugs that penetrate conductors, allowing for efficient manufacturing and reduced area size without compromising the memory cell array structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged three-dimensionally, then storage capacity is improved, but area size increases
Solution Approach 1:
The patent transitions from two-dimensional planar arrangement to three-dimensional vertical stacking of memory cells. Multiple memory cell layers are stacked along the vertical direction, with each layer containing memory cells formed over different regions of the substrate. This dimensional change enables significantly increased storage capacity while maintaining a compact footprint area.
Solution Approach 2:
The patent implements a nested structure where multiple memory cell layers are stacked vertically, with each layer containing memory cells that are spatially arranged to overlap or interleave with adjacent layers. The conductive structures and insulating layers are also nested within each other, creating a compact three-dimensional configuration that maximizes storage density within the available area.
2Area of stationary object
If conductors are arranged in a staggered pattern, then space utilization is improved, but manufacturing complexity increases
Solution Approach 1:
The conductor structures are segmented into multiple distinct layers and types, including first conductors forming word lines, second conductors forming bit lines, third conductors forming source lines, and fourth conductors forming drain lines. Each conductor type is formed in a separate manufacturing step with specific patterning and deposition processes, allowing independent optimization of each conductor layer while achieving the overall staggered three-dimensional arrangement.
Solution Approach 2:
The patent employs three-dimensional staggered arrangement of conductor layers, where conductors in different layers are positioned at offset horizontal locations. This vertical stacking with horizontal staggering creates efficient space utilization by allowing multiple conductor paths to coexist in a compact volume, reducing the planar area required for interconnect structures.
Data Source
AI summary
Each of first conductors arranged in a first direction has a first portion not covered by an adjacent first conductor. A memory pillar extending in the first direction is in contact with the first conductors. A third conductor extending in the first direction has a lower surface in contact with the first portion of one of the first conductors. A fourth conductor penetrates the first portion of a fifth conductor which is one of the first conductors and at least one sixth conductor closer to a side of a second direction than the fifth conductor. The side surface of the fourth conductor is in contact with the fifth conductor. The at least one first insulator covers a surface of each of the at least one sixth conductor.