Memory Pillar Asymmetry for Structural Integrity
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Solution Overview
Problem
Current memory array technologies face challenges in achieving structural integrity and efficient storage of information due to limitations in programmable material thickness and switching characteristics, particularly in resistive RAM and phase change memory cells.
Innovation Solution
The development of memory arrays where memory cells are formed within pillars with varying peripheral configurations, allowing for thicker programmable material and improved structural integrity, enabling enhanced switching characteristics and separation between memory states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If thinner programmable material is used to achieve higher density, then storage capacity increases, but structural integrity and switching characteristics deteriorate
Solution Approach 1:
The patent transitions from planar memory structures to three-dimensional pillar structures with varying peripheral configurations. This vertical dimensionality change allows thicker programmable material to be accommodated within the pillar volume, improving structural integrity and switching characteristics while maintaining high storage density through vertical stacking of memory cells between crossing access lines.
Solution Approach 2:
The patent employs pillars with varying peripheral configurations (different cross-sectional shapes at different heights) rather than uniform cylindrical pillars. This asymmetric design optimizes the structural integrity and electrical characteristics of the programmable material, allowing thicker material deposition while maintaining reliable switching behavior between memory states.
2Strength
If thicker programmable material is used to improve structural integrity, then switching characteristics improve, but storage density decreases
Solution Approach 1:
By utilizing vertical pillars extending through multiple layers with crossing access lines, the patent achieves three-dimensional memory cell arrangement. This allows thicker programmable material within each cell while maintaining high density through the vertical stacking approach and cross-point architecture where memory cells are formed at intersections of word and bit lines.
3Ease of manufacture
If uniform pillar structures are used for simplicity, then manufacturing ease improves, but structural integrity and switching characteristics worsen
Solution Approach 1:
The patent employs pillars with varying peripheral configurations (different cross-sectional shapes at different heights) rather than uniform cylindrical pillars. This asymmetric design optimizes the structural integrity and electrical characteristics of the programmable material, allowing thicker material deposition while maintaining reliable switching behavior between memory states.
Data Source
AI summary
Some embodiments include a memory array having a first series of access/sense lines which extend along a first direction, a second series of access/sense lines over the first series of access/sense lines and which extend along a second direction substantially orthogonal to the first direction, and memory cells vertically between the first and second series of access/sense lines. Each memory cell is uniquely addressed by a combination of an access/sense line from the first series and an access/sense line from the second series. The memory cells have programmable material. At least some of the programmable material within each memory cell is a polygonal structure having a sidewall that extends along a third direction which is different from the first and second directions. Some embodiments include methods of forming memory arrays.