Memory Pillar Integration in Embedded Devices
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Solution Overview
Problem
In advanced CMOS technology nodes, the integration of memory pillars with taller bottom electrodes into back-end-of-line (BEOL) interconnect structures is challenging due to dielectric material gouging during etching, which increases the total height of the memory pillar and makes it difficult to fit between conductive lines, leading to potential exposure of the memory stack.
Innovation Solution
The method involves forming a memory pillar with a bottom electrode, memory stack, and top electrode, encapsulating it with layers to protect the stack, and using ion beam etching to pattern the pillar and form trenches around it, allowing the pillar to protrude into the top conductive line, ensuring the top electrode contacts the conductive line at the sidewall and part of the pillar penetrates into it, thus accommodating taller bottom electrodes without recessing or etching conductive lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If ion beam etching is used to pattern the memory pillar and form trenches, then the memory pillar can be effectively fitted between conductive lines, but dielectric material gouging occurs which increases the total height of the memory pillar
Solution Approach 1:
The patent allows the memory pillar to extend vertically beyond the typical interconnect spacing by having it protrude into the top conductive line. This dimensional adjustment resolves the contradiction by accommodating the increased height caused by dielectric gouging while maintaining proper electrical connections through sidewall contact geometry.
Solution Approach 2:
The patent creates localized differentiating features: the memory pillar has enhanced conductivity at its upper portion where it contacts the top conductive line, and the top conductive line is designed with specific geometry to accommodate the protruding pillar. This local quality adjustment ensures reliable electrical connection despite the increased overall height.
2Adaptability or versatility
If the memory pillar height increases due to dielectric material gouging, then taller bottom electrodes can be integrated, but the memory pillar becomes difficult to fit between conductive lines
Solution Approach 1:
The patent employs a dynamic design where the memory pillar's upper portion is allowed to protrude into and contact the top conductive line, rather than being constrained to a fixed position between conductive lines. This dynamic adaptation enables integration of taller bottom electrodes while maintaining manufacturability through self-adjusting contact geometry.
3Reliability
If the memory pillar protrudes into the top conductive line, then reliable contact is ensured, but the top conductive line may reach the memory stack causing exposure
Solution Approach 1:
The patent introduces the top conductive line as an intermediary element that makes controlled contact with the memory pillar's upper portion. This intermediary contact ensures reliable electrical connection while the dielectric material and encapsulation layers continue to protect the memory stack, preventing direct exposure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows the memory pillar to be effectively fitted between conductive lines, preventing the top conductive line from reaching the memory stack and ensuring reliable contact, thereby addressing the issue of dielectric material gouging and enabling the integration of taller memory pillars in advanced CMOS technology.
Implementation Method 1
using ion beam etching to pattern the pillar and form trenches around it
Data Source
AI summary
A semiconductor device includes a base structure of an embedded memory device including a bottom electrode contact (BEC) landing pad within a memory area of the embedded memory device and a first metallization level having at least a first conductive line within a logic area of the embedded memory device, a cap layer disposed on the base structure, a BEC disposed through the cap layer on the BEC landing pad, a memory pillar disposed on the BEC and the cap layer, encapsulation layers encapsulating the memory pillar to protect the memory stack, and a second metallization level including a second conductive line surrounding the top electrode, a via disposed on the first conductive line such that the second via is below the top electrode, and a third conductive line disposed on the via to enable the memory pillar to be fitted between the first and second metallization levels.