Memory Cell Pillar Structure to Prevent Seam-Induced Bridging
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Solution Overview
Problem
As semiconductor devices undergo continual reductions in minimum feature size, the formation of dielectric pillars with high aspect ratios often results in seams, leading to a risk of bridging during the formation of conductive pillars in memory cells, which can affect the integrity and controllability of memory cell behavior.
Innovation Solution
A pull-back process is implemented to address the seams issue in dielectric pillars, ensuring controllable cell behavior by forming gap filling pillars between conductive pillars, which prevents bridging and maintains the integrity of memory cell structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dielectric pillars with high aspect ratios are formed to increase integration density, then manufacturing precision is improved, but seams appear in the dielectric pillars leading to bridging risks
Solution Approach 1:
A gap filling pillar is introduced as an intermediary structure between the first and second conductive pillars. This gap filling pillar fills the gap between conductive pillars and prevents conductive material from bridging through seams in the dielectric pillars during formation, thereby resolving the reliability issue while maintaining high aspect ratio dielectric pillars
Solution Approach 2:
The gap filling pillar is formed preliminarily before forming the conductive pillars. By pre-filling the gap with dielectric material and creating the gap filling pillar structure first, the patent prevents potential bridging issues that would occur during subsequent conductive pillar formation, addressing the reliability concern before it can manifest
2Productivity
If minimum feature size is reduced to increase integration density, then productivity is improved, but seams form in dielectric pillars affecting cell behavior controllability
Solution Approach 1:
The gap filling pillar serves as an intermediary that blocks seams in the dielectric pillars from causing bridging between conductive pillars. This allows the patent to maintain reduced minimum feature sizes for high integration density while preventing seam-related defects through the gap filling structure
3Reliability
If gap filling pillars are formed between conductive pillars to prevent bridging, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent segments the dielectric material formation into multiple stages: first forming dielectric pillars, then forming the gap filling pillar in the gap between conductive pillars, and finally forming conductive pillars. This segmentation allows the gap filling pillar to be integrated into the existing structure without requiring complete redesign, thereby limiting the increase in device complexity
Data Source
AI summary
A memory device includes a plurality of first conductive pillars, a plurality of second conductive pillars, a plurality of gap filling pillars, a channel layer and first dielectric pillars. The gap filling pillars are located in between the first conductive pillars and the second conductive pillars. The channel layer is extending in a first direction, and located on side surfaces of the first conductive pillars and the second conductive pillars. The first dielectric pillars are located in between the channel layer and the plurality of gap filling pillars, wherein a length of an interface where the first dielectric pillars contact the gap filling pillars along the first direction is different from a length of the gap filling pillars along the first direction.