3D Memory Pillar Channel Structure for Reliable Cell Operation
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Solution Overview
Problem
There is a need to improve the operation characteristics of memory cells in three-dimensional nonvolatile memory devices, particularly in terms of their arrangement and structural integrity.
Innovation Solution
A semiconductor memory device is designed with a stacked body comprising alternating conductive and insulating layers, featuring pillars with a channel layer having varying grain boundaries and additive concentrations at the interface, along with a specific manufacturing process that includes metal-assisted annealing to promote crystallization and enhance the channel layer's properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a plurality of memory cells are arranged along the height direction of a pillar in three-dimensional nonvolatile memory, then storage capacity is improved, but operation characteristics of the memory cells deteriorate
Solution Approach 1:
The patent applies local quality by creating a dual-structure channel layer with different crystalline regions. A first channel layer with a first crystal orientation is formed in a lower region of the pillar, while a second channel layer with a second crystal orientation is formed in an upper region. This allows different segments of the channel to have optimized properties for different functions, improving overall memory cell operation while maintaining high storage capacity through vertical stacking
Solution Approach 2:
The channel layer is segmented into multiple regions with different crystal orientations along the height direction of the pillar. This segmentation allows each region to contribute differently to memory cell operation, with the first crystal orientation region providing certain electrical characteristics and the second crystal orientation region providing complementary characteristics, thereby improving overall operation reliability while maintaining high density
2Ease of manufacture
If the channel layer has uniform structure throughout the pillar height, then manufacturing is simplified, but memory cell operation characteristics are suboptimal
Solution Approach 1:
The patent employs preliminary action by forming a sacrificial layer with a specific crystal orientation before forming the final channel layer. The sacrificial layer is grown with a first crystal orientation, then a second channel layer with a second crystal orientation is formed over it. The sacrificial layer is subsequently removed, leaving the dual-orientation channel structure. This preliminary structuring enables complex channel properties to be achieved through sequential, manageable manufacturing steps rather than requiring complex direct formation processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the performance and reliability of memory cells by improving the crystallinity and conductivity of the channel layer, leading to better data storage and retrieval capabilities.
Implementation Method 1
a specific manufacturing process that includes metal-assisted annealing to promote crystallization and enhance the channel layer's properties
Implementation Method 2
a second semiconductor layer that extends in the stacked body in the stacking direction and includes more grain boundaries than grain boundaries of the first semiconductor layer
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked one by one, and a pillar extending in the stacked body in a stacking direction of the stacked body, in which the pillar includes a first semiconductor layer extending in the stacked body in the stacking direction, and a second semiconductor layer that extends in the stacked body in the stacking direction and includes more grain boundaries than grain boundaries of the first semiconductor layer, and an additive having a peak concentration at an interface between the first semiconductor layer and the second semiconductor layer is included.