Semiconductor Memory Pillar Structure With Segmented Charge Storage
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Solution Overview
Problem
Reducing the layer thickness of conductive layers in semiconductor memory devices to increase storage capacity leads to interference between memory cells, necessitating effective charge storage layer division for each memory cell.
Innovation Solution
A semiconductor memory device design with a stacked body structure that includes a pillar extending in the stacking direction, featuring insulating layers with a fragmented charge storage layer interposed between them, and a varying outer shape at different height positions to minimize interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the layer thickness of conductive layers is reduced to increase the number of stacked layers, then storage capacity is improved, but interference between memory cells increases
Solution Approach 1:
The charge storage layer is divided into multiple independent charge storage regions along the stacking direction, with each region corresponding to a specific memory cell. This segmentation prevents charge leakage between adjacent memory cells while maintaining thin conductive layer structures, thereby resolving the interference problem that arises when increasing storage capacity through layer stacking.
2Quantity of substance
If the number of stacked layers is increased to enhance storage capacity, then storage capacity is improved, but device complexity increases
Solution Approach 1:
The insulating layer serves multiple functions simultaneously: it provides electrical insulation between conductive layers, structurally supports the fragmented charge storage regions, and acts as a barrier to prevent charge leakage. This multi-functionality reduces the need for additional specialized layers, thereby increasing storage capacity through stacking without proportionally increasing device complexity.
3Object-affected harmful factors
If the charge storage layer is divided into multiple regions for each memory cell, then interference between memory cells is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The charge storage layer is formed as a continuous layer before being patterned into fragmented regions. The insulating layer is pre-formed with the appropriate thickness and material properties to serve as both a barrier and structural support. This preliminary formation of layers with proper specifications simplifies subsequent processing steps and reduces the precision requirements for dividing the charge storage layer into individual memory cell regions.
Data Source
AI summary
A pillar of a semiconductor memory device of an embodiment includes a semiconductor layer extending in a stacking direction in a stacked body, first and second insulating layers sequentially covering a side wall of the semiconductor layer from a semiconductor layer side, and a plurality of fragment layers each of that a third insulating layer scattered at height positions of the plurality of conductive layers interposed between the first and second insulating layers, and the first insulating layer includes a first portion in which an outer shape at a first height position located between both end portions in a thickness direction of each of the plurality of conductive layers is a first distance in a first direction along the plurality of conductive layers, and a second portion in which an outer shape at a second height position located between height positions of the both end portions of the plurality of conductive layers and the first height position is a second distance larger than the first distance in the first direction.