Bonded Memory Pillar Layout for Short-Circuit Fault Isolation
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in distinguishing between short circuit failures between bonding pads and short circuit failures between memory pillars, as the current configurations do not provide clear electrical connections that allow for such differentiation.
Innovation Solution
The semiconductor memory device is designed with a configuration where neighboring bonding pads are connected to non-neighboring memory pillars, ensuring that when a short circuit failure occurs, it can be determined whether the failure is between the bonding pads or the memory pillars based on their electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If neighboring bonding pads are connected to neighboring memory pillars, then the electrical connection is simple and direct, but it becomes impossible to distinguish between short circuit failures between bonding pads and short circuit failures between memory pillars
Solution Approach 1:
The patent divides the connection configuration into two distinct patterns: normal connections (neighboring bonding pads to neighboring memory pillars) and test connections (neighboring bonding pads to non-neighboring memory pillars). This segmentation allows the system to differentiate between bonding pad failures and memory pillar failures by switching between connection patterns, thereby resolving the inability to precisely locate faults.
2Measurement precision
If a configuration is added to enable fault differentiation, then fault detection precision improves, but device complexity increases
Solution Approach 1:
The patent introduces a dynamic switching mechanism that allows the connection pattern to change between normal operation mode and fault detection mode. During normal operation, the simple neighboring-to-neighboring connection is used. When fault detection is needed, the connection pattern dynamically switches to neighboring-to-non-neighboring configuration, enabling fault differentiation without permanently increasing device complexity.
Data Source
AI summary
A semiconductor memory device includes a first chip, a second chip, and a multiple of bonding pads. The first chip has a multiple of memory pillars that penetrate a multiple of wiring layers in a first direction. The second chip is bonded to the first chip. The multiple of bonding pads are provided at a bonding face between the first chip and the second chip. The multiple of bonding pads include a first bonding pad that electrically connects a first memory pillar among the multiple of memory pillars to one of a multiple of transistors, and a second bonding pad that neighbors the first bonding pad when seen from the first direction, and which electrically connects a second memory pillar among the multiple of memory pillars to one of the multiple of transistors. The second memory pillar does not neighbor the first memory pillar when seen from the first direction.