3D Memory Pillar Layout for Select Gate Line Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving high cell integration and efficient voltage control for selecting string units due to limitations in interconnect layer division and boron doping processes, which affect the degree of cell integration and manufacturing complexity.
Innovation Solution
The semiconductor memory device employs a configuration with stacked interconnects and memory pillars arranged in a specific pattern, allowing for electrical division of select gate lines for each string unit by controlling voltage based on threshold voltage differences, eliminating the need for dummy pillars and members that divide the select gate line, and simplifying the boron ion injection process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If interconnect layers are divided to control voltage for selecting string units, then voltage control precision is improved, but device complexity increases due to additional dummy pillars and members
Solution Approach 1:
The select gate line is electrically divided into multiple segments (first select gate line for first string units, second select gate line for second string units) by using different interconnect layers. This segmentation allows independent voltage control for different string unit groups, achieving precise voltage control without adding dummy pillars or complex structural members.
Solution Approach 2:
The patent transitions from a single-plane interconnect structure to a stacked three-dimensional interconnect structure where first and second interconnect layers are arranged at different heights. This dimensional change enables electrical division of the select gate line through vertical stacking rather than horizontal expansion, reducing device complexity while maintaining voltage control precision.
2Adaptability or versatility
If dummy pillars and members are added to divide select gate lines, then string unit selection capability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent merges the functions of dummy pillars and structural dividers into the regular memory pillar structure. The first and second memory pillars serve both as memory storage elements and as electrical dividers for the select gate lines, eliminating the need for separate dummy pillars and simplifying manufacturing processes.
Solution Approach 2:
The memory pillars are designed to serve multiple functions: they act as both memory storage structures and as electrical dividers for the select gate lines. This multi-functionality eliminates the need for dedicated dummy pillars or structural members, reducing manufacturing complexity while maintaining string unit selection capability.
3Reliability
If boron doping is applied to all memory pillars, then select transistor threshold voltage is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies boron doping selectively only to the first memory pillar, while the second memory pillar remains undoped or differently doped. This local quality approach allows different select transistors (first and second select transistors) to have different threshold voltage characteristics, improving reliability for different string unit groups without requiring high-precision uniform doping across all pillars.
Solution Approach 2:
Instead of uniformly doping all memory pillars with boron to achieve threshold voltage control, the patent inverts the approach by selectively doping only specific memory pillars (first memory pillar) while leaving others (second memory pillar) undoped or differently doped. This inverted selective doping strategy reduces manufacturing precision requirements while achieving the desired threshold voltage stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances cell integration, reduces manufacturing complexity, and allows for precise electrical division of select gate lines, improving the overall performance and efficiency of the memory device.
Implementation Method 1
The first memory pillar is doped with boron to form a first select transistor, and the second memory pillar is doped with boron to form a second select transistor
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes: stacked interconnects including a first interconnect layer and a second interconnect layer, the first interconnect layer including a first area and a second area arranged in a first direction, the second interconnect layer being arranged above the first interconnect layer in a second direction intersecting the first direction, the second interconnect layer not including the first area and including the second area; a first memory pillar arranged in the first area and passing through the first interconnect layer in the second direction; and a second memory pillar arranged in the second area and passing through the first interconnect layer and the second interconnect layer in the second direction.