Memory Pillar Contact Layout for Hole Supply in NAND Erase
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Solution Overview
Problem
In semiconductor memory devices, particularly NAND flash memory, the increasing demand for holes during data erasing poses challenges due to high integration requirements, which existing technologies struggle to address effectively.
Innovation Solution
The semiconductor memory device incorporates a configuration with a first wiring, a second wiring, a memory pillar, and a contact plug with a metal contact, where the second wiring is positioned above the first wiring, and the contact plug is in contact with the semiconductor layer below the upper surface of the second wiring, facilitating the generation of holes for efficient data erasing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high integration is implemented in semiconductor memory devices, then device density is improved, but data erasing efficiency deteriorates
Solution Approach 1:
By segmenting the bit line into multiple portions with insulating layers between them, the invention enables targeted hole injection during data erasing operations. This segmentation improves erasing efficiency in high-density regions by controlling hole distribution, preventing hole loss, and enabling faster erasure times despite the increased integration density.
2Device complexity
If the contact plug is positioned below the upper surface of the second wiring, then manufacturing complexity is reduced, but electrical connection reliability may be compromised
Solution Approach 1:
The contact plug is positioned in the vertical dimension below the upper surface of the second wiring rather than at the same level. This dimensional adjustment simplifies the manufacturing process by avoiding complex lateral alignment while maintaining reliable electrical connection through the vertical stacking architecture, which is characteristic of modern three-dimensional integrated circuit design.
Data Source
AI summary
A semiconductor memory device includes a first wiring, a second wiring, a memory pillar, a semiconductor layer, and a contact plug. The second wiring is provided above the first wiring in a first direction. The memory pillar penetrating at least one of a portion of the first wiring or a portion of the second wiring in the first direction. The semiconductor layer extends in the first direction provided in the memory pillar. The contact plug contains a metal and has a lower surface provided in the memory pillar, and the lower surface is in contact with the semiconductor layer below an upper surface of the second wiring.