3D Memory Pillar and Interconnect Layout for Dense Data Access
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in achieving high integration and large capacity while maintaining efficient data storage and retrieval operations.
Innovation Solution
A semiconductor memory device with a three-dimensional memory structure and a specific interconnect layout, including a substrate with aligned regions, interconnect layers, contacts, and memory pillars, facilitates efficient data storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensional memory structure is adopted for high integration and large capacity, then data storage capacity is improved, but device complexity increases
Solution Approach 1:
The substrate is divided into multiple regions (first region, second region with third and fourth regions) with different interconnect configurations. This segmentation allows optimization of each region for specific functions, enabling high integration while managing complexity through modular design.
Solution Approach 2:
The patent transitions from planar interconnect layouts to three-dimensional stacked interconnect layers. Multiple interconnect layers are arranged vertically with bridge portions and terrace portions, utilizing the third dimension to increase storage capacity without proportionally increasing planar complexity.
2Productivity
If interconnect layers are stacked in three dimensions with bridge and terrace portions, then integration density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The interconnect layers are designed with pre-defined bridge portions and terrace portions that are formed in specific sequences during manufacturing. The first interconnect layer's bridge portion is formed before subsequent layers, establishing a foundation that guides precise formation of overlapping and non-overlapping regions in later steps.
Solution Approach 2:
Different portions of the interconnect layers have different structural characteristics. Bridge portions provide continuous connections while terrace portions create spaced arrangements. This local differentiation allows optimized electrical connections and simplified manufacturing in each specific region rather than requiring uniform high precision throughout.
3Speed
If contacts are positioned to access specific interconnect layers in the stacked structure, then data access speed is improved, but device complexity increases
Solution Approach 1:
The first conductor acts as an intermediary element that couples multiple components: it connects to the terrace portion of the first interconnect layer, contacts the first contact, and provides coupling paths. This intermediary structure simplifies the direct routing that would otherwise be required between multiple stacked interconnect layers and contacts.
Solution Approach 2:
The first conductor serves multiple functions simultaneously: it provides electrical connection to the first interconnect layer, establishes contact with the first contact, and creates coupling paths. This multi-functionality reduces the need for separate dedicated structures for each function, thereby reducing overall device complexity while maintaining fast data access.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes: a substrate provided with a plane formed by first and second directions, and including first and second regions aligned in the first direction, the second region including third and fourth regions aligned in the second direction; interconnect layers arranged with the substrate in a third direction, being spaced from one another in the third direction, and each including a bridge portion and a terrace portion; a contact extending in the third direction; a conductor isolated from the interconnect layers excluding a first interconnect layer, and including, a first portion contacting the terrace portion of the first interconnect layer in the fourth region, a second portion contacting the contact in the third region, and a third portion coupling the first and second portions; and a memory pillar extending in the third direction in the first region.