3D Memory Pillar Interconnect Layout for High-Density Storage
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in achieving high integration and large capacity while maintaining efficient data storage and retrieval operations.
Innovation Solution
A semiconductor memory device with a three-dimensional memory structure, incorporating a first and second interconnect layer, memory pillars, and a specific layout of insulating members to enhance data storage capacity and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensional memory structure is adopted for high integration and large capacity, then storage capacity is improved, but device complexity increases
Solution Approach 1:
The memory device is divided into multiple blocks, each block containing memory pillars with memory cells. The interconnect layers are segmented into first and second interconnect layers with different routing functions. This segmentation allows complex functionality to be organized into manageable, modular units that can be independently designed and manufactured.
Solution Approach 2:
The patent transitions from planar two-dimensional memory structures to three-dimensional vertical structures. Memory pillars extend in the first direction (vertical), with memory cells formed at intersections with interconnect layers in the second direction (horizontal). This dimensional transition enables higher storage capacity within the same footprint area.
2Quantity of substance
If multiple interconnect layers are used to increase storage capacity, then storage density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The manufacturing process is divided into distinct stages: forming the first interconnect layer with first contacts, then forming the second interconnect layer with second contacts. Each layer can be manufactured and tested independently, reducing the cumulative precision requirements compared to forming all interconnect structures in a single process step.
Solution Approach 2:
The first interconnect layer and first contacts are formed before the second interconnect layer. This preliminary action allows the lower layer to serve as a foundation, with subsequent layers built upon established structures, reducing alignment and positioning precision requirements.
3Productivity
If memory pillars are arranged in three-dimensional configuration, then integration is improved, but electrical coupling efficiency may deteriorate
Solution Approach 1:
Memory cells are formed at the intersections of memory pillars (extending in the first direction) with interconnect layers (in the second direction). This three-dimensional intersection geometry ensures reliable electrical coupling between vertical memory structures and horizontal interconnect lines, maintaining signal integrity while achieving high integration.
Solution Approach 2:
The interconnect layers are positioned to specifically intersect with memory pillars at designated locations, creating localized coupling points where electrical connections are established. This local quality approach ensures efficient electrical coupling at critical interfaces while allowing flexibility in overall device layout.
Data Source
AI summary
In general, according to one embodiment, a semiconductor memory device includes: a first interconnect layer provided on a first area; a second interconnect layer arranged apart from the first interconnect layer in a first direction and provided across the first area and a second area in the first direction; a plurality of third interconnect layers provided above the second interconnect layer and spaced apart from each other in the first direction; a third insulating member dividing the second interconnect layer into first and second portions in the third direction; first and second memory pillars extending in the first direction in the first area intersecting the first and the second portion of the second interconnect layer respectively; and first and second contacts extend in the first direction in the first area, electrically coupled to the first and the second portions of the second interconnect layer, respectively.