3D Memory Pillar Structure With Low-K Isolation for Parasitic Capacitance
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Solution Overview
Problem
As the dimensions and spacing of conductive features in memory devices decrease, parasitic capacitance increases, leading to higher power demands and delays in memory devices, particularly in 3D NAND Flash memory devices.
Innovation Solution
The implementation of a microelectronic device structure with vertically alternating insulating and conductive structures, including the formation of pillar structures, conductive plug structures, and a low-K dielectric material with air gaps, which reduces parasitic capacitance by providing improved electrical properties and isolation between conductive elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the dimensions and spacing of conductive features are decreased to increase memory density, then memory density is improved, but parasitic capacitance increases leading to higher power demands and delays
Solution Approach 1:
The patent introduces low-K dielectric material as an intermediary substance between adjacent conductive features (word lines, bit lines, contact plugs). This low-K material has a dielectric constant lower than conventional dielectric materials, which reduces the parasitic capacitance formed between neighboring conductive elements. The low-K dielectric acts as a mediator that maintains electrical isolation while minimizing capacitive coupling, thereby reducing power consumption and signal delays despite the reduced spacing between conductive features.
Solution Approach 2:
The patent changes the dielectric parameter (dielectric constant K) of the insulating material between conductive features. By using materials with lower dielectric constants (low-K materials), the parasitic capacitance C = Kε₀A/d is reduced. This parameter change allows the device to maintain high memory density with closely spaced conductive features while minimizing the harmful capacitive effects that would otherwise increase power demand and cause signal delays.
2Reliability
If conventional insulating materials are used to isolate conductive features, then electrical isolation is provided, but parasitic capacitance remains high requiring increased insulating material thickness
Solution Approach 1:
The patent changes the dielectric parameter (dielectric constant) from conventional values (K > 3.0) to low-K values (K < 3.0). This parameter change reduces parasitic capacitance while maintaining adequate electrical isolation. The low-K dielectric material provides the necessary insulation between conductive features at reduced thickness, eliminating the need to increase insulating material thickness to compensate for high capacitance.
Solution Approach 2:
The patent employs composite material structures including low-K dielectric materials combined with conventional dielectric materials in different regions of the memory device. The low-K dielectric is strategically placed in regions where parasitic capacitance has the greatest impact on performance (between closely spaced word lines and bit lines), while conventional dielectric materials are used in other regions. This composite approach optimizes the balance between electrical isolation and parasitic capacitance reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces bridging and parasitic capacitance by up to 40%, leading to faster programming times and optimized RC performance, while minimizing the need for increased insulating material thickness and reducing processing complexities.
Implementation Method 1
parasitic (e.g., stray) capacitance between adjacent conductive features within the memory device increases
Implementation Method 2
a low-K dielectric material with air gaps, which reduces parasitic capacitance by providing improved electrical properties and isolation between conductive elements
Data Source
AI summary
A method of forming a microelectronic device comprises forming a stack structure comprising vertically alternating insulating structures and conductive structures arranged in tiers. Each of the tiers individually comprises one of the insulating structures and one of the conductive structures. A sacrificial material is formed over the stack structure and pillar structures are formed to extend vertically through the stack structure and the sacrificial material. The method comprises forming conductive plug structures within upper portions of the pillar structures, forming slots extending vertically through the stack structure and the sacrificial material, at least partially removing the sacrificial material to form openings horizontally interposed between the conductive plug structures, and forming a low-K dielectric material within the openings. Microelectronic devices, memory devices, and electronic systems are also described.