3D Memory Pillar Structure With Mesh Source Connection
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Solution Overview
Problem
Current semiconductor memory devices face challenges in increasing integration density due to limitations in lithography techniques, leading to issues such as damage to memory films during manufacturing and increased ON resistance in stacked type memory devices.
Innovation Solution
A semiconductor memory device with a mesh-like connecting member and silicon pillars that are integrally formed, eliminating the need to remove memory films from the bottom of through-holes and reducing the length of current paths between source and bit lines, thereby enhancing integration density and reducing ON resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory film is removed from the bottoms of through-holes to connect silicon pillars to source lines, then electrical connection is achieved, but the memory film on the side surfaces of the through-holes is damaged
Solution Approach 1:
The patent applies preliminary action by forming the memory film on the inner surfaces of through-holes before forming the silicon pillars, and then forming a recess that exposes the memory film at the bottom of the through-hole. This sequence allows the memory film to be prepared in advance and only selectively removed where needed, preventing damage to the memory film on the side surfaces while achieving the necessary electrical connection.
2Quantity of substance
If the number of memory cells connected in series between source lines and bit lines is increased, then integration density is improved, but ON resistance increases and control circuit size increases
Solution Approach 1:
The patent applies dimensionality change by transitioning from a planar memory structure to a three-dimensional stacked structure with through-holes extending vertically through multiple layers. This allows memory cells to be arranged in three dimensions rather than just two, increasing integration density without proportionally increasing the number of series-connected cells between source and bit lines, thereby maintaining lower ON resistance.
Data Source
AI summary
A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.