Semiconductor Memory Pillar Etching via Metal Catalyst
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Solution Overview
Problem
Current semiconductor memory devices face challenges in manufacturing cost due to the need for expensive vacuum apparatuses for dry etching and individual etching processes for hole and line shapes, which increase unit costs and can lead to shape variations and increased interconnect resistance.
Innovation Solution
The use of metal-assisted chemical etching (MaCE) for wet etching allows for simultaneous etching of hole and line shapes, reducing manufacturing costs and maintaining a 90-degree angle, while also enabling the formation of memory pillars with uniform interconnect layers that cover memory pillars, thereby reducing stress and improving chip integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dry etching is used for etching hole and line shapes, then etching precision is improved, but manufacturing cost increases due to expensive vacuum apparatuses and individual etching processes
Solution Approach 1:
The patent replaces the mechanical vacuum-based dry etching system with a chemical wet etching system. Specifically, it uses metal-assisted chemical etching (MaCE) where a metal catalyst layer enables selective etching of silicon regions. This substitution eliminates the need for expensive vacuum apparatuses while achieving comparable etching precision through chemical reactions that selectively remove material based on the presence of the metal catalyst.
Solution Approach 2:
The patent applies a single wet etching process that simultaneously etches both hole shapes and line shapes, replacing the need for separate individual etching processes required in conventional dry etching methods. The metal catalyst pattern serves as a universal etching mask that defines both hole and line regions, allowing one process to perform multiple etching functions, thereby reducing manufacturing complexity and cost.
2Manufacturing precision
If individual etching processes are used for hole and line shapes, then shape precision is improved, but productivity decreases due to multiple processing steps
Solution Approach 1:
The patent merges the etching processes for hole shapes and line shapes into a single unified wet etching step. By using a metal catalyst layer that is selectively deposited in both hole and line regions, the process achieves shape precision comparable to individual etching while doubling productivity through simultaneous formation of both feature types in one processing cycle.
Solution Approach 2:
The metal catalyst pattern serves as a universal etching template that defines both hole and line geometries. This multi-functional approach allows a single etching process to create multiple feature types with precise dimensional control, eliminating the need for separate process steps for different feature geometries.
3Ease of manufacture
If non-uniform interconnect layers are formed over memory pillars, then manufacturing simplicity is improved, but interconnect resistance increases and chip integrity deteriorates
Solution Approach 1:
The patent applies local quality by forming the interconnect layer with uniform thickness specifically in the regions over the memory pillars, while allowing different thickness or configuration in other areas. This is achieved through controlled deposition or planarization processes that ensure uniform coverage where needed for electrical performance, while maintaining manufacturing simplicity elsewhere. The uniform interconnect layer over pillars reduces resistance and stress concentration, improving chip reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach lowers the manufacturing cost of semiconductor memory devices by using inexpensive wet etching apparatuses, reduces shape variations, and suppresses increases in interconnect resistance, allowing for efficient and cost-effective production of three-dimensionally stacked NAND type flash memory.
Implementation Method 1
a metal catalyst layer corresponding to the hole shape and the line shape is formed on the stacked body of the semiconductor layers
Implementation Method 2
the insulating layer in the memory pillar region is removed
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes: first and second interconnect layers; a plurality of third interconnect layers stacked between the first and second interconnect layers; a first insulating layer passing through the plurality of third interconnect layers, and including one end that is in contact with a first face of the first interconnect layer; a first memory pillar including a first semiconductor layer passing through the plurality of third interconnect layers and a charge storage layer provided between the plurality of third interconnect layers and the first semiconductor layer. A distance between a third face of the first interconnect layer opposite to the first face and the second interconnect layer in the first direction, differs at a position corresponding to the first insulating layer from at positions corresponding to the third interconnect layers.