3D Memory Pillar Alignment Using Tailored Reticle Openings
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Solution Overview
Problem
Conventional methods for forming microelectronic devices, such as 3D NAND memory devices, face challenges with pillar bending and misalignment, leading to increased electrical resistance and capacitance, which affect device performance, reliability, and durability, and result in defects like access line contact over etch stresses and current leaks.
Innovation Solution
The use of tailored reticles to form openings and elliptical openings in microelectronic device structures, accommodating observed pillar bending, improves the alignment and overlap between pillars and conductive contacts, reducing dummy pillar areas and enhancing electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional formation methods are used to increase memory density with vertical memory arrays, then memory density increases, but pillar bending and misalignment occur leading to increased electrical resistance and capacitance
Solution Approach 1:
The patent applies preliminary action by forming compensation features (dummy pillars or adjusted staircase structures) during the fabrication process before final electrical connections are established. These compensation features pre-correct for the expected pillar bending that will occur during subsequent processing, thereby maintaining alignment between access lines and memory strings despite the bending.
Solution Approach 2:
The patent implements preliminary anti-action by introducing compensation features that counteract the harmful effect of pillar bending before it impacts electrical connections. The dummy pillars or adjusted staircase structures are positioned to offset the bending displacement, creating a pre-counterbalancing effect that maintains proper alignment.
2Reliability
If access lines are formed to connect to conductive structures, then electrical connections are established, but access line contact over etch stresses and current leaks occur
Solution Approach 1:
The patent uses compensation features as intermediary structures between the access lines and the memory strings. These dummy pillars or adjusted staircase structures serve as mediators that improve the alignment and overlap between access lines and conductive structures, thereby reducing current leakage paths and improving electrical connection reliability.
3Reliability
If word line electrical resistance and capacitance are decreased, then device performance improves, but pillar bending in areas adjacent to staircase structures increases
Solution Approach 1:
The patent applies local quality by making the staircase structure non-uniform - specifically, the height of the staircase steps is adjusted locally in different regions. The steps closer to the memory strings are made taller than those farther away, creating a gradient that compensates for pillar bending in the critical regions while maintaining proper electrical connections.
Data Source
AI summary
A method of forming a microelectronic device including a first stack structure comprising alternating levels of insulative structures and other insulative structures, forming strings of memory cells through the first stack structure, forming a second stack structure over the first stack structure, based at least partially on observed amount of pillar bending within the first stack structure, forming a first tailored reticle specific to the observed amount of pillar bending, utilizing the first tailored reticle to form openings extending through the second stack structure and over some of the strings of memory cells, wherein centers of the openings over the strings of memory cells are at least substantially aligned with the centers of uppermost surfaces of the strings of memory cells in a direction of the observed pillar bending, and forming upper pillars extending through the second stack structure and over some of the strings of memory cells.