3D Memory Pillar Layout With Insulator-Separated Row Spacing
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Solution Overview
Problem
Existing semiconductor storage devices face challenges in miniaturization due to restrictions on the spacing distance between bit lines, which limits the arbitrary selection of pillar arrangements.
Innovation Solution
The semiconductor storage device incorporates a configuration with multiple rows of pillars and an insulator that separates conductor layers into regions, allowing for a variable interval between pillars in different rows to optimize spacing and miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the spacing distance between bit lines is reduced to achieve device miniaturization, then the device size is reduced, but the arrangement of pillars becomes restricted and cannot be arbitrarily selected
Solution Approach 1:
The bit line array is divided into multiple groups, with each group containing multiple bit lines. Within each group, bit lines are arranged at a first pitch, while groups are arranged at a second pitch in the first direction. This segmentation allows independent optimization of pillar arrangements within each group, providing design flexibility despite reduced overall spacing.
Solution Approach 2:
Different regions of the device employ different pillar arrangement strategies. Specifically, pillars connected to bit lines within the same group can have different spacing configurations compared to pillars connected to bit lines in different groups. This local differentiation enables optimized electrical characteristics in each region while maintaining compact overall device dimensions.
2Volume of moving object
If the spacing distance between bit lines is reduced to achieve device miniaturization, then the device size is reduced, but the fabrication process complexity increases
Solution Approach 1:
The fabrication process is segmented into distinct stages corresponding to the formation of different bit line groups and their associated pillars. This allows each group to be fabricated with optimized process parameters, making the overall complex structure manufacturable through modular processing steps.
Solution Approach 2:
The patent utilizes vertical stacking of conductor layers and pillars in the third direction (vertical dimension) to achieve high integration. By arranging bit line groups and pillars in multiple vertical layers, the device achieves miniaturization without requiring excessively small lateral spacing, thereby simplifying fabrication processes.
Data Source
AI summary
A semiconductor storage device includes a plurality of conductor layers that are stacked in a first direction and a plurality of bit lines that are spaced from each other in a second direction. Pillars extend in the first direction through the conductor layers and are electrically connected to the bit lines. An insulator is provided that divides the region in which the plurality of pillars are disposed into adjacent regions. An interval between the pillars in an end row adjacent to the insulator is greater than an interval between the pillars in an inner row that is not directly adjacent to the insulator.