3D Memory Pillar Insulation Layout for Precise Selective Etching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor memory devices face challenges in achieving high integration density and capacity while maintaining efficient data storage and retrieval operations, particularly in three-dimensional memory configurations.
Innovation Solution
A semiconductor memory device with a specific layered structure comprising interconnect layers, insulating films, and memory pillars that include a charge storage film and insulating films, where the insulating films are designed with varying etching rates to enhance manufacturing precision and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensional memory configuration is adopted, then integration density and capacity are improved, but manufacturing precision and process control become more difficult
Solution Approach 1:
The patent applies local quality by differentiating the etching rates of insulating films in different regions. Specifically, the first insulating film has a lower etching rate than the second insulating film, allowing selective etching in different areas during manufacturing. This enables precise control of the memory pillar structure formation while maintaining the three-dimensional configuration for high integration density.
2Manufacturing precision
If insulating films with different etching rates are used, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent segments the insulating film structure into multiple types with different etching rates. The first insulating film and second insulating film are distinct layers with deliberately different etching characteristics, allowing selective removal during manufacturing. This segmentation enables precise formation of the memory pillar while keeping the overall device structure manageable through systematic organization of these segmented layers.
Data Source
AI summary
In general, according to one embodiment, a semiconductor memory device includes: stacked layers including a plurality of interconnect layers and first insulating films alternately stacked in a first direction; a memory pillar extending and passing through the stacked layers in the first direction, wherein the memory pillar includes a semiconductor, a second insulating film provided between the semiconductor and the stacked layers, a charge storage film provided between the second insulating film and the stacked layers, a plurality of third insulating films provided between the charge storage film and the interconnect layers, and a plurality of fourth insulating films provided between the charge storage film and the first insulating films; and a fifth insulating film having a lower etching rate to hydrofluoric acid than the fourth insulating films, provided to cover side surface of the interconnect layers.