Semiconductor Memory Pillar Shape Control via Dummy Stepped Region
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Solution Overview
Problem
The challenge in semiconductor memory devices is to reduce chip size while maintaining the integrity of the memory cell array structure, particularly in ensuring the shape and alignment of memory pillars and slits, which is complicated by processing unevenness at the cyclic ends of patterns during etching.
Innovation Solution
Incorporating a dummy stepped region within the dummy block to guarantee the shape of memory pillars and slits, reducing the need for external dummy patterns that would increase chip size, and optimizing the arrangement of memory pillars and support pillars to minimize chip expansion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dummy patterns are added outside the block to guarantee the shape of memory pillars and slits, then the shape and alignment of memory pillars and slits are ensured, but the chip size increases
Solution Approach 1:
The patent merges the dummy block with the stepped structure by forming the stepped structure within the dummy block itself, rather than adding separate dummy patterns outside the block. This integration ensures the shape of memory pillars and slits at the block end while avoiding additional chip area expansion.
Solution Approach 2:
The patent utilizes the vertical dimension by creating a stepped structure with multiple levels within the dummy block. This three-dimensional approach allows the dummy block to serve dual purposes: maintaining pattern shape integrity and minimizing horizontal area occupation.
2Area of stationary object
If the chip size is reduced, then manufacturing costs are reduced, but the structural integrity of the memory cell array may be compromised
Solution Approach 1:
The patent performs preliminary shaping of the dummy block into a stepped structure before forming memory pillars and slits. This preliminary action ensures that the etching process maintains proper shape and alignment of memory structures at the block end, preserving structural integrity without requiring additional dummy patterns that would increase chip size.
Solution Approach 2:
The patent applies the stepped structure specifically to the dummy block region where shape control is most critical, while maintaining standard structure elsewhere. This localized quality enhancement ensures structural integrity at the block end without unnecessarily complicating or expanding the entire chip structure.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a substrate, insulating members, first conductive layers, first pillars, and second pillars. The substrate includes a first area, a second area, block regions, and a first dummy block region. The insulating members are arranged at respective boundary portions of the block regions and the first dummy block region. The first conductive layers are partitioned by the insulating members. The first pillars penetrates the first conductive layers in a region where the first area and the block regions overlap. The second pillars penetrates at least one of the first conductive layers in a region where the first area and the first dummy block region overlap.