Memory Pillar Size Variation for Uniform Channel Length
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Solution Overview
Problem
Existing memory arrays with stacked pillars face challenges in maintaining consistent programming and erase properties due to variations in cross-sectional areas and channel lengths across memory cells, leading to differences in electron storage capacity and retention time.
Innovation Solution
The design involves a memory cell adjacent to a semiconductor pillar where the pillar size decreases from top to bottom, with corresponding increases in channel length, ensuring consistent channel lengths and electron storage volumes across memory cells, thereby maintaining uniform programming and erase properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the cross-sectional area of the semiconductor pillar is reduced to increase memory density, then the memory density is improved, but the channel length becomes inconsistent across memory cells leading to non-uniform programming and erase properties
Solution Approach 1:
The patent applies local quality by making the semiconductor pillar have different cross-sectional areas at different vertical positions. The pillar has a larger cross-sectional area at the top and a smaller cross-sectional area at the bottom, creating locally optimized structures. This allows memory cells at different heights to have appropriate channel dimensions while maintaining overall density, directly resolving the contradiction between density improvement and channel length uniformity.
2Reliability
If the pillar size varies to accommodate different memory cell positions, then the memory cell uniformity is improved, but the device structure becomes more complex
Solution Approach 1:
The patent segments the semiconductor pillar into different vertical zones with distinct cross-sectional areas. The pillar is divided into a top portion with larger area and a bottom portion with smaller area, with each segment serving specific memory cells. This segmentation approach achieves uniform memory cell characteristics across different positions while maintaining a relatively simple continuous pillar structure, balancing reliability improvement with structural simplicity.
Data Source
AI summary
The disclosure is related to memory arrays and methods. One such memory array has a substantially vertical pillar. A memory cell adjacent to the pillar where the pillar has a first size has a greater channel length than a memory cell adjacent to the pillar where the pillar has a second size larger than the first size.