Memory Cell Pillar Source Junction Plug for 3D NAND
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Solution Overview
Problem
The challenge in fabricating memory devices with increased storage capacity is maintaining reliable memory operations while managing the complexity of multiple levels of memory cells, which affects the overall density and performance of electronic systems.
Innovation Solution
A 3D memory device fabrication process involving a memory cell stack with a common cell pillar, using alternating layers of dielectric and conductor materials, and forming a conductive plug to enhance the overlap of source and select gate materials, thereby improving string current and threshold voltage, is employed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cell levels is increased to accommodate increased storage capacity, then storage capacity is improved, but fabrication complexity and reliability maintenance become more challenging
Solution Approach 1:
The memory device is divided into multiple stacks, each containing multiple memory cells arranged in a three-dimensional configuration. Each stack is further segmented into selective gates, control gates, and charge storage structures that can be independently formed and controlled. This segmentation allows complex memory operations to be broken down into manageable components, facilitating fabrication while maintaining high storage capacity.
Solution Approach 2:
The patent transitions from planar two-dimensional memory cell arrangements to three-dimensional vertical stacks. Memory cells are arranged vertically with selective gates extending in the vertical dimension, allowing multiple memory cells to occupy the same footprint area. This dimensional change dramatically increases storage capacity without proportionally increasing fabrication complexity, as the same fabrication processes can be applied repeatedly to form each level of the stack.
2Quantity of substance
If the number of memory cell levels is increased to accommodate increased storage capacity, then storage capacity is improved, but maintaining reliable memory operations becomes more challenging
Solution Approach 1:
Different regions of the memory device are assigned different functional qualities. Selective gates in different stacks can have different doping types (n-type or p-type) to optimize for specific operations. Control gates are positioned at specific locations to provide localized control over charge storage structures. This local differentiation allows each component to be optimized for its specific function, maintaining reliability across the entire multi-level memory structure.
Solution Approach 2:
The fabrication process forms the complete three-dimensional stack structure, including all selective gates, control gates, and charge storage structures, before final memory operations begin. Tunneling structures are pre-formed between control gates and charge storage structures to enable subsequent charge injection and erasure operations. This preliminary formation of all structural elements ensures that the complex multi-level structure is already in place and properly configured before data operations commence, improving operational reliability.
3Reliability
If conductive plug is formed to enhance overlap of source and select gate materials, then string current and threshold voltage are improved, but manufacturing process complexity increases
Solution Approach 1:
The conductive plug merges the source material with the select gate material, creating a continuous conductive path that enhances the overlap between these components. This merging eliminates the need for separate source and select gate regions, simplifying the overall structure while improving electrical characteristics. The conductive plug is formed as a single continuous element that simultaneously provides source contact and select gate functionality, reducing manufacturing steps compared to forming separate structures.
Solution Approach 2:
The conductive plug acts as an intermediary element that connects the source material to the select gate structure. It mediates the electrical connection between these components, ensuring proper current flow and voltage control. The conductive plug material is chosen to provide optimal electrical properties, serving as a bridge that enhances the interaction between source and select gate while maintaining manufacturing simplicity through a single formation step.
Data Source
AI summary
Some embodiments include apparatuses and methods having a source material, a dielectric material over the source material, a select gate material over the dielectric material, a memory cell stack over the select gate material, a conductive plug located in an opening of the dielectric material and contacting a portion of the source material, and a channel material extending through the memory cell stack and the select gate material and contacting the conductive plug.