Memory Pillar Spacer Structure for Leak-Safe Word Line Isolation
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Solution Overview
Problem
Current semiconductor memory devices face challenges in preventing current leaks between contact plugs and word lines due to inadequate spacer configurations, leading to reduced yield and potential excessive etching of support pillars during manufacturing.
Innovation Solution
The semiconductor memory device employs a spacer configuration comprising a first spacer with a lower etching rate and a second spacer with a higher etching rate, strategically positioned to prevent current leaks and control etching depths, allowing for dense support pillar placement without restriction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single uniform spacer is used, then the structure is simple, but current leaks occur between contact plugs and word lines
Solution Approach 1:
The spacer is divided into two distinct segments: a first spacer with a first etching rate and a second spacer with a second etching rate different from the first. This segmentation allows each spacer portion to perform its specific function - the first spacer prevents current leaks between contact plugs and word lines, while the second spacer controls etching depth, thereby resolving the contradiction between reliability and complexity.
Solution Approach 2:
Different portions of the spacer structure are assigned different etching rates to match local functional requirements. The first spacer (with first etching rate) is positioned where current leak prevention is critical, while the second spacer (with second etching rate) is positioned where etching depth control is needed. This local differentiation resolves the contradiction by optimizing each region for its specific purpose.
2Manufacturing precision
If etching is performed deeply to remove insulators, then insulator removal is complete, but support pillars are excessively etched
Solution Approach 1:
The second spacer with the second etching rate is formed in advance to establish a predetermined etching stop position. During the etching process, this second spacer prevents excessive etching of the support pillar by stopping the etchant at the appropriate depth, thereby ensuring complete insulator removal while protecting support pillar integrity.
Solution Approach 2:
The second spacer acts as an intermediary layer between the etchant and the support pillar. It controls the etching process by providing a predetermined stop position, allowing complete removal of insulators while preventing excessive etching of the support pillar, thus resolving the contradiction between manufacturing precision and reliability.
3Productivity
If support pillars are placed densely, then device integration is high, but current leaks occur between contact plugs and word lines
Solution Approach 1:
The segmented spacer structure with different etching rates enables dense support pillar placement while maintaining current leak prevention. The first spacer with the first etching rate specifically addresses current leak prevention in high-density configurations, allowing the device to achieve high integration without sacrificing reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses current leaks and prevents excessive etching, maintaining the functionality of contact plugs while allowing for flexible support pillar placement, thereby enhancing manufacturing yield and device performance.
Implementation Method 1
The first spacer includes a first portion provided between the second spacer and the conductor, a second portion provided between the second spacer and the contact plug, and a third portion provided between the support pillar and the contact plug, and the first spacer has a shape that recedes from the contact plug toward the conductor, and the first spacer offers an etching rate smaller than an etching rate of the second spacer
Data Source
AI summary
A semiconductor memory device according to an embodiment includes a first conductor, first to third insulators, a second conductor, and a memory pillar. The first conductor and the first insulator are arranged in a first direction. The second conductor extends in the first direction to penetrate the first conductor and the first insulator. The memory pillar extends in the first direction to penetrate the first conductor and the first insulator, and includes a semiconductor. The second insulator is provided between the first conductor and the second conductor. The third insulator includes a first portion between the second insulator and the first conductor, a portion on a surface on one side of the second insulator in the first direction, and a portion on a surface on the other side of the second insulator in the first direction. The third insulator offers an etching rate smaller than the second insulator.