3D Memory Pillar Wiring Layout for Lower Chip Area and Resistance

The patent transitions from conventional planar (2D) memory string arrangements to a three-dimensional stacked architecture where memory pillars extend vertically through multiple wiring layers. This dimensional change allows current paths to be optimized in the vertical direction while reducing horizontal spread, thereby decreasing channel resistance without increasing chip footprint area.

The patent implements a nested structure where memory pillars are positioned to penetrate through multiple stacked wiring layers (first wirings, second wirings, third wirings). The memory pillars are nested within the vertical stack of wirings, allowing efficient vertical integration and reduced current path length compared to planar arrangements.

The patent divides the memory structure into distinct functional segments: first wirings for initial memory strings, second wirings for additional memory strings, and third wirings for further expansion. Each wiring layer is independently formed with its own pattern formation and etching processes, allowing modular manufacturing that scales density while managing complexity through standardized repetitive steps.

The patent resolves manufacturing complexity by transitioning to vertical stacking where multiple wiring layers are formed in the thickness direction. This allows memory density to increase vertically rather than requiring proportional increases in planar area, enabling higher density with manageable process complexity through sequential layer formation.