Memory Device PIM Address Generation for Lower Communication Overhead
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Solution Overview
Problem
Existing random access memory systems face inefficiencies due to the need for significant communication between the central processing unit and memory, leading to bottlenecks in processing operations.
Innovation Solution
A memory device with integrated processing-in-memory (PIM) capabilities, featuring a control logic with a PIM address generator that generates new column addresses based on partial column addresses, allowing for enhanced in-memory processing through a second operation mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the memory device operates in traditional mode sending all column address bits to memory banks, then address accuracy is maintained, but communication overhead increases and processing efficiency decreases
Solution Approach 1:
The patent extracts certain column address bits from the traditional address transmission path and uses them as row address bits for selecting calculation result storage locations. This extraction reduces the number of bits that need to be communicated between the memory controller and memory banks, thereby reducing communication overhead and improving processing efficiency while maintaining address accuracy through the alternative addressing mechanism.
2Loss of energy
If the memory device performs calculations externally, then address routing is simple, but communication between CPU and memory increases creating bottlenecks
Solution Approach 1:
The patent merges the calculation function with the memory device by integrating calculation units within the memory architecture. This allows calculations to be performed directly within the memory device, eliminating the need for continuous data transfer between CPU and memory, thereby reducing communication energy loss. The dual operation modes (traditional and PIM modes) enable the memory device to handle both conventional memory operations and in-memory processing.
3Productivity
If the PIM address generator uses remaining column address bits to generate PIM addresses, then in-memory processing is enhanced, but address generation complexity increases
Solution Approach 1:
The patent implements a universal address generation mechanism where the PIM address generator can operate in multiple modes. In traditional operation mode, it passes column address bits directly to memory banks. In PIM operation mode, it generates PIM addresses by combining row address bits with remaining column address bits. This multi-functionality allows the same hardware structure to support both conventional memory access and in-memory processing without requiring separate complex addressing logic.
Data Source
AI summary
Disclosed is a memory device which includes a plurality of memory banks and control logic. The control logic receives a plurality of column address bits and a plurality of read commands. The control logic includes a processing-in-memory (PIM) address generator. In a first operation mode, the control logic sends the plurality of column address bits to a memory bank. In a second operation mode, when the PIM address generator receives a first read command of the plurality of read commands, the control logic sends, to the memory bank, a first PIM address generated based on remaining column address bits other than some column address bits of the plurality of column address bits.