Memory Pin Multiplexing With PAM Signaling for Faster Data Transfer
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Solution Overview
Problem
Existing memory devices face challenges in increasing data transfer rates and reducing power consumption while maintaining reliability, particularly in multiplexing distinct signals on a single pin, which can lead to increased error rates and manufacturing costs due to complex interconnects.
Innovation Solution
Implementing multi-symbol signaling using a modulation scheme with at least three levels to multiplex first and second data in a single signal, transmitted across internal signal paths within a memory device, reducing the need for multiple interconnects and enhancing read and write speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple distinct signals are multiplexed on a single pin of a memory device, then data transfer rate is improved and power consumption is reduced, but error rate increases and manufacturing complexity increases
Solution Approach 1:
The patent segments the signaling protocol into distinct phases (read phase, write phase, refresh phase) that are sequentially transmitted over the single pin. Each phase is clearly delimited by control signals, allowing the receiver to properly interpret the multiplexed data without confusion, thereby maintaining reliability while achieving high data transfer rates.
Solution Approach 2:
The patent employs periodic clock signals and structured timing sequences to organize the multiplexed data transmission. By using periodic cycles with defined states (e.g., idle states, data transfer states, refresh states), the system ensures that each signal type is transmitted in its designated time window, preventing signal confusion and reducing errors.
2Ease of manufacture
If multiple distinct signals are multiplexed on a single pin of a memory device, then the number of internal interconnects is reduced and manufacturing cost decreases, but device complexity increases
Solution Approach 1:
The patent implements a universal single pin interface that performs multiple functions (reading, writing, refreshing, status reporting) that would traditionally require separate dedicated pins. The pin dynamically switches between these functions based on control signals, eliminating the need for multiple physical interconnects and reducing manufacturing complexity despite the increased signal processing requirements.
Solution Approach 2:
The patent employs dynamic signal routing and adaptive protocol selection where the single pin's function changes in real-time based on operational mode. The memory device dynamically adjusts its communication protocol depending on whether it is in read mode, write mode, or refresh mode, allowing one pin to replace multiple static connections.
3Speed
If multi-symbol signaling with at least three levels is used, then read and write speeds are improved, but signal integrity requirements increase
Solution Approach 1:
The patent utilizes multi-level voltage signaling where different voltage levels represent different data states (e.g., 0V for logic 0, 0.6V for logic 1, 1.2V for logic 2 in PAM3 encoding). By changing the voltage parameter to have multiple discrete levels instead of binary, the system achieves higher data rates per symbol while maintaining robust signal detection through the defined voltage thresholds.
Data Source
AI summary
Methods, systems, and devices for multiplexing distinct signals on a single pin of a memory device are described. Techniques are described herein to multiplex data using a modulation scheme having at least three levels. The modulated data may be communicated to multiple memory dies over a shared bus. Each of the dies may include a same or different type of memory cell and, in some examples, a multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the modulated signal may be configured to represent a plurality of bits of data.