Memory Controller Pin Power Gating Using Split Control and Data Queues
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Solution Overview
Problem
Existing memory systems face challenges in reducing power consumption, particularly in battery-powered devices like mobile devices and IoT devices, where power management is crucial.
Innovation Solution
A memory controller with separate queues for control information and data transmission information, allowing independent power control to each pin, reducing power consumption by shutting off power to idle pins based on queue states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power is continuously supplied to all pins for reliable communication, then communication reliability is maintained, but power consumption increases
Solution Approach 1:
The pin set is segmented into multiple groups based on their functional roles (control pins, data pins, clock pins). Power control is applied independently to each group based on the operational state of the memory interface, allowing selective power supply to only the necessary pin groups at any given time, thus reducing overall power consumption while maintaining communication reliability.
Solution Approach 2:
The power supply state of each pin group is dynamically adjusted based on the operational mode of the memory interface. The controller monitors the activity state of different pin groups and switches their power supply states accordingly - supplying power when active and shutting off when idle, thereby adapting power consumption to actual communication needs.
2Use of energy by moving object
If power is shut off to pins to reduce power consumption, then power efficiency improves, but communication latency increases
Solution Approach 1:
The controller performs preliminary actions by pre-charging or pre-activating pin groups that are expected to be needed soon based on the command queue state. When a write command is detected, the data pin group is pre-prepared for data transmission. This preliminary preparation minimizes the activation delay when power needs to be supplied, thereby reducing latency while still maintaining power-saving states during idle periods.
Solution Approach 2:
The power control operates periodically by monitoring the state of command and data queues at regular intervals. Based on this periodic assessment, the controller adjusts the power supply state of pin groups, switching between active and power-saving modes in a rhythmic pattern that balances power consumption with communication responsiveness.
3Device complexity
If separate queues for control and data information are implemented, then power control precision improves, but system complexity increases
Solution Approach 1:
The information queue is segmented into two separate queues: a control information queue for commands and addresses, and a data information queue for actual data transmission. This segmentation allows the power controller to independently manage power supply to control pins and data pins based on the presence and state of information in each respective queue, achieving precise power control without requiring complex integrated management systems.
Data Source
AI summary
Provided is a memory controller including an interface including a plurality of pins configured to communicate with a memory apparatus, a queue manager configured to control a first queue to store control information for controlling an operation of the memory apparatus storing or reading data and a second queue to store data transmission information for controlling transmission of the data, and an interface controller configured to shut off power to at least one pin among the plurality of pins based on the first queue and the second queue.