3D U-Shaped Memory Pipe Cell Erase Operation
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Solution Overview
Problem
In semiconductor memory devices, particularly 3D structured memory devices, cell current stability is a design consideration due to limitations in reducing memory device size, and existing technologies face challenges in efficiently performing erase operations to maintain data integrity and prevent pipe cell deterioration.
Innovation Solution
A semiconductor memory device with a memory string and peripheral circuit, featuring a pipe cell, multiple memory cells arranged in a vertical U-shaped structure, where the peripheral circuit performs an erase operation on the pipe cell by supplying hot holes to the channel layers, reducing threshold voltages and ensuring stable cell current through controlled voltage applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory device size is reduced to increase degree of integration, then device density improves, but cell current stability deteriorates
Solution Approach 1:
The patent transitions from planar 2D memory cell arrangement to a 3D vertical structure where memory cells are stacked above each other in a columnar arrangement. This dimensional change allows higher density while maintaining adequate current paths through the vertical channel, resolving the contradiction between density and current stability.
Solution Approach 2:
The memory array is segmented into multiple independent memory strings, each with its own select transistors and channel. This segmentation isolates current paths, preventing interference between adjacent cells and maintaining stable cell currents even as overall device density increases through vertical stacking.
2Reliability
If erase operation is performed on pipe cell separately, then data integrity improves, but operation complexity increases
Solution Approach 1:
The patent merges the pipe cell erase operation with the memory cell erase operation into a single unified process. By applying the erase voltage to both pipe cells and memory cells simultaneously through shared control lines, the patent maintains data integrity without increasing operational complexity.
Solution Approach 2:
The select transistors and control circuits are designed with multi-functionality, serving both memory cell selection and pipe cell erase functions. This universal design allows the same hardware to perform multiple operations without requiring separate dedicated circuits, thereby maintaining simplicity while ensuring data integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution stabilizes cell current and improves memory device reliability by performing erase operations on pipe cells during memory cell erase operations, preventing pipe cell deterioration and maintaining data integrity, thus enhancing the degree of integration and performance of memory devices.
Implementation Method 1
performing an erase operation on the pipe cell by supplying hot holes to the channel layers, reducing threshold voltages
Data Source
AI summary
A semiconductor memory device includes a memory string and a peripheral circuit. The memory string has a pipe cell, a plurality of memory cells, and at least one channel layer having a three-dimensional U-shaped structure. The peripheral circuit is configured to perform an erase operation on the pipe cell. A method of operating the semiconductor memory device includes selecting the memory string and performing the erase operation on the pipe cell.