Semiconductor Memory Pipe Latch Circuit Duty Cycle Control

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Solution Overview

Problem

Conventional semiconductor memory devices face issues with deteriorated duty characteristics and jitter in data output due to transistor coupling loading, particularly in high-frequency and low-power environments, affecting operation reliability and stability.

Innovation Solution

The semiconductor memory device incorporates an output control signal generation circuit, a pipe latch circuit, and a synchronization circuit to generate and synchronize data output signals with internal clocks, using enable signals to control transistor operations and improve duty characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If transistors are used in the trigger circuit for data output, then data can be synchronized with internal clocks, but transistor coupling loading deteriorates duty characteristics and introduces jitter

Engineering Contradiction:

Improveoperation reliabilityVSAvoidduty characteristics

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The patent extracts the problematic transistor coupling loading from the trigger circuit by using separate pull-up and pull-down transistor groups that are controlled independently. This separation removes the harmful coupling effect while maintaining the necessary data synchronization function.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent segments the transistor coupling loading into separate pull-up and pull-down transistor groups. By dividing the single coupling function into two independent groups, each controlled by different enable signals, the patent eliminates the detrimental interaction between pull-up and pull-down transistors that caused duty characteristic deterioration and jitter.

Inventive Principle:

Principle #1Segmentation

2Reliability

If transistor size is increased to reduce coupling loading effects, then data output stability improves, but device area and power consumption increase

Engineering Contradiction:

Improvedata output stabilityVSAvoiddevice area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent makes the transistor groups dynamically controllable through enable signals (first enable signal for pull-up, second enable signal for pull-down). This dynamic control allows the transistors to be activated only when needed, reducing the required transistor size while maintaining data output stability through precise timing control.

Inventive Principle:

Principle #15Dynamics

3Device complexity

If conventional trigger circuit is used, then device complexity is reduced, but duty characteristic deterioration and jitter occur in high-frequency and low-power environments

Engineering Contradiction:

Improvecircuit complexityVSAvoidoperation stability

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The patent creates a multi-functional trigger circuit that can operate in different modes (normal data output mode and ODT mode) by controlling the enable signals. The same transistor groups serve both as data output drivers and as ODT (On-Die Termination) elements, eliminating the need for separate circuits and maintaining simplicity while improving reliability.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS8780646B2Semiconductor memory device

Publication Date: 2014.07.15 MIMIRIP LLC

AI summary

A semiconductor memory device includes a pipe latch circuit configured to receive parallel input data and output serial data or set an output terminal of the pipe latch circuit at a predetermined voltage level in response to an enable signal, and a synchronization circuit configured to output an output data of the pipe latch circuit in synchronization with an internal clock.