Memory-in-Pixel Layout for Full Grayscale in Compact Displays
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Solution Overview
Problem
Memory-in-pixel displays require a large number of memory cells per pixel for full grayscale resolution, leading to increased pixel area consumption and making it difficult to meet target area specifications for competitive products.
Innovation Solution
A compact memory-in-pixel display structure is implemented using a fully-depleted semiconductor-on-insulator processing technology platform, where each pixel block includes an array of memory cells over a Pwell, an LED driving circuit over an adjacent Nwell, and a logic circuit with P-type transistors over the Nwell and N-type transistors over the Pwell, allowing for a compact layout without breaks between wells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a large number of memory cells per pixel is used for full grayscale resolution, then grayscale resolution is improved, but pixel area consumption increases
Solution Approach 1:
The patent combines the memory cell array and LED driving circuit into a single integrated block structure where memory cells are positioned over Pwells and driving circuits over adjacent Nwells within the same pixel area. This merging allows full grayscale resolution (12+ memory cells) to be achieved without increasing overall pixel area, as both functions share the same spatial footprint through integrated layout
Solution Approach 2:
The patent utilizes vertical integration by stacking multiple functional layers above the semiconductor substrate. Memory cells, driving circuits, and logic circuits are arranged in three-dimensional space with different layers performing different functions, effectively increasing the functional density within the two-dimensional pixel area and enabling high-resolution grayscale without lateral area expansion
Data Source
Figure 1
Figure 2A~2B
Figure 3A
AI summary
Disclosed are a pixel and a compact memory-in-pixel display (e.g., implemented in a fully-depleted semiconductor-on-insulator processing technology platform). A block of electronic components for a pixel includes a memory cell array, a driving circuit for an LED, and a logic circuit connected between the memory cell array and driving circuit. The memory cell array is above a Pwell, the driving circuit is above an adjacent Nwell, and the logic circuit includes P-type transistors on the Nwell and N-type transistors on the Pwell. A pixel array is above alternating P and N wells with a single buried Nwell below. Specifically, each column of pixels is above adjacent elongated P and N wells and, within each column, adjacent pixels have mirrored layouts. Furthermore, adjacent columns of pixels are above two elongated wells of one type and a shared elongated well of the opposite type therebetween and the adjacent columns have mirrored layouts.