Semiconductor Memory Plane Address Comparator Read Latency
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently managing read operations during write operations, leading to increased read latency and processing inefficiencies due to the need for different read modes based on matching or non-matching plane addresses.
Innovation Solution
A semiconductor memory device with a PB address comparator and controller that compares plane addresses to determine whether to execute a first or second read operation, allowing for efficient data reading by saving or bypassing write data depending on address matches, thereby reducing read latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a read operation is executed during a write operation in the same plane, then read latency increases due to data conflict, but if the read operation is suspended, then processing efficiency decreases
Solution Approach 1:
The patent segments the memory device into multiple independent planes (PB0-PB7), allowing simultaneous write operations in one plane and read operations in another plane without data conflict. The controller can suspend a write operation in a first plane and execute a read operation in a second plane, thereby reducing read latency while maintaining processing efficiency through parallel operation of different planes.
2Adaptability or versatility
If different read modes are implemented based on plane address matching, then read operation flexibility improves, but device complexity increases
Solution Approach 1:
The patent implements a plane address comparator that preliminarily compares the plane address of the read operation with the plane address of the suspended write operation before executing the read operation. Based on the comparison result, the controller selectively executes either a first read mode (when addresses match) or a second read mode (when addresses differ). This preliminary address comparison enables flexible read operation selection while maintaining relatively simple device architecture through straightforward address matching logic.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes: planes each including a memory cell array including memory cells; a comparator configured to, when suspending a write operation and executing a read operation, compare a first plane address corresponding to the write operation with a second plane address corresponding to the read operation; and a controller configured to suspend the write operation and execute the read operation. The controller is configured to, based on an output signal from the comparator, execute the first read operation when the first and second plane addresses match, and execute the second read operation when the first and second plane addresses differ.