Memory Die Plane Balancing for Consistent Write Access
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Solution Overview
Problem
Memory systems experience performance issues due to imbalanced planes, leading to inconsistent access metrics and reduced efficiency as the memory die approaches capacity, which is exacerbated by indiscriminate data transfer operations.
Innovation Solution
The memory system balances planes by identifying and avoiding one or more imbalanced planes during data transfer operations, ensuring that data is written to the remaining planes to maintain even distribution of available blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is written to all planes indiscriminately during transfer operations, then the memory system can maintain high throughput, but plane imbalance occurs leading to inconsistent access metrics and reduced efficiency
Solution Approach 1:
The patent applies local quality by treating different planes differently based on their individual block availability status. Instead of uniform data distribution across all planes, the system identifies planes with insufficient available blocks and excludes them from receiving data during transfer operations, thereby maintaining local balance in each plane while preserving overall system throughput
2Reliability
If the memory system avoids imbalanced planes during data transfer, then access consistency improves, but the number of available planes for writing decreases
Solution Approach 1:
The patent implements dynamics by making the set of active planes configurable and adaptive. The plane exclusion configuration allows the system to dynamically adjust which planes are excluded from data transfer based on real-time block availability monitoring, enabling the system to optimize between access consistency and throughput depending on the current memory state
3Quantity of substance
If the memory die approaches capacity, then storage utilization increases, but plane imbalance is exacerbated leading to reduced write efficiency
Solution Approach 1:
The patent applies preliminary action by proactively monitoring block availability in each plane before initiating data transfer operations. The system identifies planes that are approaching capacity and excludes them in advance from receiving data, preventing the exacerbation of plane imbalance before it occurs and maintaining write efficiency even as storage utilization increases
Data Source
AI summary
Methods, systems, and devices for plane balancing in a memory system are described. A memory system may select a memory die for writing a set of data. The memory die may include a plurality of planes each of which may include a respective plurality of blocks of memory cells. Based on selecting the memory die, the memory system may determine a first plane of the plurality of planes that has a first quantity of blocks with an availability status and a second plane of the plurality of planes that has a second quantity of blocks with the availability status. The memory system may write the set of data to the plurality of planes, excluding at least the first plane, based at least in part on the first quantity of blocks and the second quantity of blocks.