Memory Plane Merge Circuits for Reliable Fixed-Line Data Transfer
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Solution Overview
Problem
Existing memory devices face limitations in data transfer due to a fixed number of data lines, leading to inefficiencies in utilizing multiple memory areas, which can result in merge failures during compression read operations.
Innovation Solution
Implementing a memory device architecture with memory planes sharing peripheral circuits, compressing circuits to compress data, merge circuits to merge compressed data, and an output buffer circuit to latch and output merged data, allowing simultaneous use of multiple memory areas with a reduced number of data lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory areas share a fixed quantity of data lines through time division multiplexing, then the number of data lines can be reduced, but merge failures occur during compression read operations
Solution Approach 1:
The patent divides memory banks into different merge groups (first merge group and second merge group) with separate merge circuits for each group. This segmentation allows independent handling of compressed data from different memory banks, preventing merge failures by ensuring that operations in one group do not interfere with operations in another group, thus maintaining reliability while using shared data lines.
Solution Approach 2:
The patent introduces separate merge circuits as intermediary components between the compressing circuits and the output buffer circuit. These merge circuits act as mediators that properly manage and combine compressed data from different memory banks before output, ensuring reliable merge operations even when multiple memory areas share the same data lines through time division multiplexing.
2Device complexity
If multiple memory planes share peripheral circuits, then device complexity is reduced, but data transfer efficiency may be limited by fixed data line quantity
Solution Approach 1:
The patent implements dynamic merge group configuration where memory banks can be flexibly assigned to different merge groups based on operational requirements. The merge circuits can dynamically handle different combinations of compressed data from various memory banks within the shared peripheral circuit structure, maintaining data transfer efficiency despite the reduced complexity from sharing peripheral circuits.
Solution Approach 2:
The shared peripheral circuits are designed with universal functionality to handle operations for multiple memory planes. The merge circuits can process compressed data from any combination of memory banks across different memory planes, making the peripheral circuits multi-functional and adaptable to various data transfer scenarios without requiring dedicated circuits for each plane.
3Adaptability or versatility
If compressed data from multiple memory banks is merged using shared data lines, then data handling capability is improved, but merge failures may occur
Solution Approach 1:
The patent segments memory banks into distinct merge groups with dedicated merge circuits for each group. This segmentation enables the system to handle compressed data from multiple memory banks simultaneously or sequentially without interference, improving data handling capability while preventing merge failures through isolated processing paths.
Solution Approach 2:
The patent implements control logic that monitors and coordinates merge operations across different merge groups. This feedback mechanism ensures that compressed data from multiple memory banks is properly managed and merged without conflicts, maintaining both high data handling capability and merge operation reliability by adjusting operations based on current system state.
Data Source
AI summary
A memory device includes a plurality of memory planes, each including a plurality of memory banks; one or more plane groups, each comprising at least two memory planes sharing at least one peripheral circuit; a plurality of compressing circuits, each connected to a corresponding memory bank and outputting compressed data by compressing data read from the corresponding memory bank; a plurality of merge circuits, each receiving compressed data and at least one output control signal corresponding to a merge group of a plurality of merge groups, each merge circuit outputting, in response to at least one output control signal, merged data obtained by merging compressed data corresponding to memory banks grouped in the merge group; and an output buffer circuit latching and outputting the merged data in response to at least one output control signal. The merge group comprises at least two memory banks in a same plane group.