Non-volatile Memory Plane Power Distribution Control
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Solution Overview
Problem
Non-volatile memory devices face challenges in managing peak power intervals across multiple memory planes, leading to potential power overload and reduced reliability due to overlapping peak power consumption periods.
Innovation Solution
A non-volatile memory device with a control circuit that monitors and controls the operations of multiple memory planes to distribute peak power intervals, using monitoring signals to delay or suspend operations and prevent complete overlap of peak power consumption periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple memory planes operate simultaneously to increase throughput, then productivity is improved, but power consumption peaks exceed supply limits causing reliability degradation
Solution Approach 1:
The control circuit implements periodic action by distributing peak power intervals of different memory planes across different time periods. Instead of allowing all memory planes to operate at peak power simultaneously, the system schedules their peak operations sequentially, ensuring that at any given time, only a subset of memory planes are in peak power consumption mode. This temporal distribution maintains high overall throughput while preventing power supply overload.
2Use of energy by stationary object
If peak power intervals are distributed across memory planes, then power consumption is controlled within supply limits, but operational complexity increases due to monitoring and coordination requirements
Solution Approach 1:
The control circuit is segmented into multiple control logic units, with each control logic unit responsible for monitoring and coordinating the operation of a specific memory plane. This segmentation allows the complex power distribution task to be divided into manageable sub-tasks, where each control logic unit independently tracks its assigned memory plane's peak power intervals and coordinates with others to achieve overall power balance. This modular approach reduces the complexity burden on any single control unit while maintaining system-wide power control.
3Device complexity
If all memory planes operate independently without coordination, then device complexity is minimized, but power overload occurs during simultaneous peak power intervals
Solution Approach 1:
The control circuit merges the monitoring and coordination functions of multiple memory planes into a unified control structure. Rather than keeping each memory plane completely independent, the system combines their control logic to collectively manage peak power intervals. This merging allows the system to maintain relatively simple individual plane operations while achieving coordinated power distribution through the integrated control circuit that oversees all planes collectively.
Data Source
AI summary
A non-volatile memory device having a memory chip is provided. The memory chip having a memory cell array including a plurality of memory planes sharing a pad, the pad configured to communicate input and output signals. The memory chip also having a control circuit configured to monitor operations of the plurality of memory planes, and control an operation of at least one of the plurality of memory planes based on a result of the monitoring such that peak power intervals of the plurality of memory planes are at least partially distributed.