Non-Volatile Memory Plane Segmentation for Random Read Bandwidth
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Solution Overview
Problem
Current semiconductor memory systems face challenges in achieving high random read processing bandwidth without increasing the number of planes per memory die, as increasing planes leads to larger die size and higher costs, and can lower die yield.
Innovation Solution
The technology concurrently reads portions of pages from separate blocks within the same plane, effectively doubling or quadrupling random read processing bandwidth by reading data from multiple blocks in parallel without adding more planes, allowing a four-plane memory die to operate like an eight or sixteen plane die in terms of random read bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of planes per memory die is increased to achieve high random read processing bandwidth, then random read bandwidth is improved, but die size increases and manufacturing cost increases
Solution Approach 1:
The memory plane is segmented into multiple independent blocks (first block, second block, etc.), each capable of independent read operations. This allows parallel read operations within a single plane without requiring additional planes, thereby increasing random read bandwidth while maintaining the same die size.
Solution Approach 2:
The patent introduces a new dimension of parallelism by enabling concurrent read operations across multiple blocks within the same plane. Instead of adding planes (vertical dimension), the solution exploits the block dimension within existing planes to achieve multi-dimensional parallelism and increase bandwidth.
2Productivity
If the number of planes per memory die is increased to achieve high random read processing bandwidth, then random read bandwidth is improved, but die yield decreases
Solution Approach 1:
By segmenting the plane into multiple independent blocks that can operate in parallel, the system achieves high bandwidth without increasing the number of planes. This segmentation approach maintains die simplicity and improves yield while still providing the desired performance through intra-plane parallelism.
3Productivity
If the number of planes per memory die is increased to achieve high random read processing bandwidth, then random read bandwidth is improved, but manufacturing cost increases
Solution Approach 1:
The plane is divided into multiple independently operable blocks that can perform parallel reads. This segmentation enables high bandwidth performance using the existing plane structure, avoiding the need to manufacture additional planes and thereby reducing manufacturing costs.
Solution Approach 2:
Each block within the plane is designed to be universally functional, capable of independent read operations. This multi-functionality allows any block to service read requests, enabling parallel operations without requiring specialized additional planes, thus reducing manufacturing complexity and cost.
Data Source
AI summary
An apparatus includes a control circuit and a plurality of non-volatile memory cells arranged in a plane of a memory die. The plane includes a first word line including a first word line portion coupled to a corresponding first group of the non-volatile memory cells, and a second word line including a second word line portion coupled to a corresponding second group of the non-volatile memory cells, the second word line different from the first word line. The control circuit is configured to apply a first voltage to the first word line portion and apply a second voltage to the second word line portion to concurrently read the first group of the non-volatile memory cells and the second group of the non-volatile memory cells. The first group of the non-volatile memory cells and the second group of the non-volatile memory cells each store less than a page of data.