Memory Plane Read Control for Sequential Cache Compatibility
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Solution Overview
Problem
Existing memory systems face challenges in performing read operations in async multi-plane independent read mode, particularly when transitioning from normal or random cache reads to sequential cache reads, due to the lack of address information in read instructions, leading to incompatibility and reduced reading performance.
Innovation Solution
The proposed solution involves a memory system and method that updates address information for memory pages after completing a read operation, allowing for sequential cache reads by including additional instructions to determine and update the addresses of memory pages, thereby enabling compatibility between async multi-plane independent read mode and sequential cache reads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If normal read or random cache read is performed in async multi-plane independent read mode, then read operation can be completed, but sequential cache read cannot be performed due to lack of address information in read instructions
Solution Approach 1:
The patent applies preliminary action by updating the address information to the next memory page address before the sequential cache read operation is actually needed. The peripheral circuit automatically increments the address pointer after each read operation completes, so when sequential cache read is initiated, the address information is already prepared and available, enabling seamless sequential access across multiple memory pages in async multi-plane independent read mode
2Adaptability or versatility
If address information is updated after each read operation to enable sequential cache read, then sequential cache read becomes compatible with async multi-plane independent read mode, but the system complexity increases
Solution Approach 1:
The peripheral circuit implements self-service by automatically updating the address information without requiring external intervention or complex control logic. The address pointer is automatically incremented after each read operation, and the peripheral circuit autonomously manages the address sequence for sequential cache read operations, reducing the need for additional control mechanisms while maintaining the enhanced functionality
Data Source
AI summary
The present disclosure provides a memory and an operation method thereof, and a memory system. The memory may include a memory cell array and a peripheral circuit coupled to the memory cell array. The memory cell array may include a plurality of memory planes. Each of the memory planes may include a plurality of memory pages. The peripheral circuit may be configured to, during performing a read operation in an async multi-plane independent read mode, read a first memory page, and update address information to address information of a memory page next to the first memory page after the read operation on the first memory page. The first memory page may be a first memory page to be read in a currently selected memory plane. The peripheral circuit may be configured to perform sequential cache read on the currently selected memory plane according to the updated address information.