Memory Plane Control with Parallel State Machines
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Solution Overview
Problem
The serial processing of control commands for different memory planes in semiconductor memory devices results in a slow overall processing rate and redundant waiting time, leading to low access efficiency.
Innovation Solution
Implementing a memory device with a peripheral circuit containing multiple state machines, each corresponding to a memory plane, allowing for parallel processing of control commands and asynchronous operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If control commands for different memory planes are processed serially, then resource conflict is avoided, but overall processing rate decreases and waiting time increases
Solution Approach 1:
The control command processing function is segmented into multiple independent state machines, with each state machine dedicated to processing commands for a specific memory plane. This segmentation allows parallel processing of commands across different planes while maintaining resource isolation, thus resolving the contradiction between avoiding resource conflicts and improving processing rate.
Solution Approach 2:
Each state machine is designed as a universal processing unit that can handle various types of control commands (read, write, erase, etc.) for its assigned memory plane. This multi-functionality allows the system to process diverse commands in parallel without requiring separate dedicated circuits for each command type, improving overall processing rate while maintaining resource conflict avoidance.
2Reliability
If control commands for different memory planes are processed serially, then resource conflict is avoided, but waiting time increases
Solution Approach 1:
By dividing the control command processing into separate state machines for different memory planes, the system eliminates the sequential waiting time that occurs when a single processor handles all planes one after another. Each plane can be serviced simultaneously, dramatically reducing total waiting time while maintaining resource conflict avoidance through dedicated processing paths.
Solution Approach 2:
The parallel state machine architecture enables continuous processing of control commands across all memory planes without idle waiting periods. While one plane is being serviced, other planes can simultaneously receive and process commands, ensuring that the system remains continuously productive and minimizing overall waiting time.
3Productivity
If multiple state machines are implemented for parallel processing, then processing speed improves, but device complexity increases
Solution Approach 1:
The control logic is segmented into multiple identical state machine modules, each handling a specific memory plane. This modular segmentation improves processing speed through parallel execution while containing complexity within each module, making the overall system more manageable despite the increase in the number of components.
Solution Approach 2:
The system transitions from a single-state-machine architecture to a multi-state-machine architecture by changing the parameter of processing parallelism. This parameter change enables simultaneous command processing for multiple planes, improving processing speed while the modular nature of state machines helps manage the resulting complexity through standardized, repeatable units.
Data Source
AI summary
A memory device, a method for controlling the memory device, and a memory system are provided. The memory device includes a memory array comprising a plurality of memory planes, and a peripheral circuit configured to control the plurality of memory planes to perform asynchronous operations. The peripheral circuit comprises a plurality of state machines connected to a memory interface of the memory device. Each state machine is configured to be associated with one or more assigned memory planes of the plurality of memory planes. Each state machine is further configure to receive, from the memory interface in parallel with other state machines, a corresponding sequence of control commands of the one or more assigned memory planes; and independently process the corresponding sequence of control commands to obtain control information of the one or more assigned memory planes.